About Cell_based Design flow

[zackwang]

I have one problem.

When I use cell_based design flow, I have some macro.

When I pre-simulation RTL-code , I can use behavior model for macro.

But I want to post-sim for SDF back-annotation, how can I treat it?

 

[kwkam]

You have get the spice file for the cell model. And then put it together with the cell netlist with loading.

 

[linuxluo]

HI,
when I do gatelevel sim, I still use macro behavioral code .I think the code of macro have time information ,and can be used in gate sim.
my macro are RAM, ROM, PLL.

 

[yasonwang]

SPEF files

Spice backannotation may be too slow. The popular flow is to extract parasitics after IP merging to obtain a SPEF file. And then by using an advanced timing delay calculator, a SDF file can be generated for your post-layout simulation.

Complement for linuxluo's gatelevel simulation.

 

[masters_yam]

hi :
i think you can change some macro to behavior model in your nelist.

masters_yam

 

[zackwang]

>Spice backannotation may be too slow. The popular flow is to extract >parasitics after IP merging to obtain a SPEF file. And then by using an >advanced timing delay calculator, a SDF file can be generated for your >post-layout simulation.

>Complement for linuxluo's gatelevel simulation.

But I think this is very strange.

I write behavior code for my macro.

I want to SDF to backannotation to behavior code??

or I only have timing Arc for macro's pin .

 

[Nobody]

A sram macro is nothing but a behavior with specify block for timing annotation . If you can characherize your macro cell , simply backannotate the timing into your own specify block . The corner case have much wide timing span ( as high as twice ) . Dont expect too much the precision in your simulation .

 

[linuxluo]

Hi, zackwang
the behavior code I mention is provided by foundry,not your design. And in it ,including detail timing information. So don't use sdf backannotation for this code.

 

[philewar]

I have one problem.

When I use cell_based design flow, I have some macro.

When I pre-simulation RTL-code , I can use behavior model for macro.

But I want to post-sim for SDF back-annotation, how can I treat it?

Hello

If you do not have any detail model for your macro, go on with your behaviour model.

 

[sandusty]

Hi, zackwang:

Treat your macro as a big NAND gate to run the rtl or the gate level simulations. If your IP provider is good enough, it should not have any problem.