realtek
Member level 5
Sorry , as a digital design beginning Guy , pls allow me to ask some stupid Question:
How to embadded Altera IP ( like LPM_fifo.lpm_rom,lpm_ram,Nios...)
in RTL code when do FPGA verify (can compiler by nc-verilog/VCS and can generate fsdb for Debussy )??
Is there any detail document tell people how to do this step by step??
How to embadded Altera IP ( like LPM_fifo.lpm_rom,lpm_ram,Nios...)
in RTL code when do FPGA verify (can compiler by nc-verilog/VCS and can generate fsdb for Debussy )??
Is there any detail document tell people how to do this step by step??