gaom9
Full Member level 4
1.3g vco
Hi,
I am working on a Δ-Σ Fractional-N Frequency Synthesizers for 1.2G-1.4G application. Before this, I have finished a Frequency Synthesizers for 2.4G-2.7G application and it works well. But when I design this new Frequency Synthesizers based on the finished one, I met a strange question about the VCO design which did not meet before.
In the Frequency Synthesizers for 1.2G-1.4G, the VCO is separated into 8 bands by a 3-bits capacitance array. The PSS results of this VCO is shown as follow which contains its load capacitance effect.
000 1.16G-1.246G
001 1.182G-1.273G
010 1.205G-1.302G
011 1.23G-1.333G
100 1.256G-1.365G
101 1.284G 1.401G
110 1.314G-1.439G
111 1.346G-1.481G
and the phase noise is -129dBc/Hz@1MHz offset. I think this VCO works well and I added it to the PLL (this PLL structure is based on the one I have finished and only change the filter and VCO)and set a test frequency to 1.3GHz. First, I chose the 100 VCO band but I found the PLL can not be locked, and the control voltage of it dropped to near 0.2V, then I tried the other bands and find it could lock at 010 band(the control voltage is 1.1V, the VDD of it is 1.8V). After tring other test frequencies, I got a conclusion that the VCO worked on a much higher frequency region than the PSS result in the PLL system. I made a tran simulation to the VCO separately, and found it works as the PSS result, not the same as the PLL system. And then I add a ideal VCO written by Verilog-A(1.256G-1.365G) to it, it could lock at 1.3G.
What a strange question it is! Does anyone meet it before? Why?
Thank you!
Best regards!
Hi,
I am working on a Δ-Σ Fractional-N Frequency Synthesizers for 1.2G-1.4G application. Before this, I have finished a Frequency Synthesizers for 2.4G-2.7G application and it works well. But when I design this new Frequency Synthesizers based on the finished one, I met a strange question about the VCO design which did not meet before.
In the Frequency Synthesizers for 1.2G-1.4G, the VCO is separated into 8 bands by a 3-bits capacitance array. The PSS results of this VCO is shown as follow which contains its load capacitance effect.
000 1.16G-1.246G
001 1.182G-1.273G
010 1.205G-1.302G
011 1.23G-1.333G
100 1.256G-1.365G
101 1.284G 1.401G
110 1.314G-1.439G
111 1.346G-1.481G
and the phase noise is -129dBc/Hz@1MHz offset. I think this VCO works well and I added it to the PLL (this PLL structure is based on the one I have finished and only change the filter and VCO)and set a test frequency to 1.3GHz. First, I chose the 100 VCO band but I found the PLL can not be locked, and the control voltage of it dropped to near 0.2V, then I tried the other bands and find it could lock at 010 band(the control voltage is 1.1V, the VDD of it is 1.8V). After tring other test frequencies, I got a conclusion that the VCO worked on a much higher frequency region than the PSS result in the PLL system. I made a tran simulation to the VCO separately, and found it works as the PSS result, not the same as the PLL system. And then I add a ideal VCO written by Verilog-A(1.256G-1.365G) to it, it could lock at 1.3G.
What a strange question it is! Does anyone meet it before? Why?
Thank you!
Best regards!