A simple Verilog question about rising edge of a signal

nervecell_23 · Aug 23, 2013

Hi guys,

I want to set a signal HIGH for only one clock cycle at the rising edge of another signal, can I use the following code?

Code:

always@((posedge clk)&&(posedge SIGNAL))
begin
    .......
end

Thanks!

pedroromanvr · Aug 24, 2013

Can you explain it more? Do you want to set a signal using two clocks?

vardan · Aug 25, 2013

Assume you need an edge detecting circuit.

Code:

assign out = Q1 & (!Q2);
always @(posedge clk or negedge rst)
	if (!rst)
		begin
			Q1 <= 1'b0;
			Q2 <= 1'b0;
		end
	else
		begin
			Q1 <= In;
			Q2 <= Q1;
		end

manu.srg · Aug 26, 2013

I think you can. But how you are going to limit it for one clock cycle?

A simple Verilog question about rising edge of a signal

nervecell_23

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pedroromanvr

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vardan

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manu.srg

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A simple Verilog question about rising edge of a signal

nervecell_23

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