A simple question about ring oscillator but trouble me

[incol]

Razavi's book said that if the gain of the delay cell (fig 1) is low, the ring oscillator can't oscillate, the gain A=[µ0(W/L0) / µ2(W/L2)]½, so we should increase W/L0 to let it oscillate, but I find that if I increase the bias current, it can also oscillate. The gain of the delay cell doesn't increase, how can it oscillate?

 

[incol]

anyone can help me?

 

[sunking]

what the gain is of this figure?
It is bigger than 1.

 

[incol]

what the gain is of this figure?
It is bigger than 1.

the gain of the delay cell is A=[µ0(W/L0) / µ2(W/L2)]½, yes, it is bigger than 1, otherwise it can't oscillate. But I din't know why I increase the bias current, it can also oscillate, the gain didn't increase at this time.

 

[sunking]

add a initial condition and try.
such as the initial voltage of out1 is "high" while out 2 is "low"

 

[incol]

add a initial condition and try.
such as the initial voltage of out1 is "high" while out 2 is "low"

I had already add a initial voltage in out1. I want to know why I increase the bias current, it oscillates, the gain didn't increase at this time.

 

[pengboy]

i dont think the Gain formula is accurate, if you in crease the biase current, usually the gm is creased and hence increase the gain.

 

[sunking]

in fact, increase the current the gain increase too.
do you consider the rds of M2 and M3?

 

[incol]

in fact, increase the current the gain increase too.
do you consider the rds of M2 and M3?

yes, thank you!
another question: when I run the corner simulation, I found the gain is too small in mos_fs, and in mos_ss, M5 will go into linear, because vcc is only 2.7v. I think this delay cell cann't meet my request, so could anybody introduce a better delay cell to me? thanks!

 

[sunking]

m5 go into linear will not affect more performance.
and increase w/l of m1 to m3 maybe help

 

[incol]

m5 go into linear will not affect more performance.
and increase w/l of m1 to m3 maybe help

but the simulation result told me that when vcc=2.7v, the bias current decreased very much, and frequency decreased, when vcc=5.5v, it worked well. I think this is because M5 came into linear when vcc=2.7v.

 

[sunking]

why not increase the W/L of all the cmos?
it seem that the Vds too big for all cmos.
and you can use current source load for it.

 

[incol]

why not increase the W/L of all the cmos?
it seem that the Vds too big for all cmos.
and you can use current source load for it.

if I increase the W/L of all the cmos, the parasitic capacitor will increase, and the frequency will decrease, so I have to increase the bias current, I think this is no useful.
and what do you mean current source load for it?

 

[Alles Gute]

If M2 and M3 have independant gate bias voltage, they are current source load. Two minimum inverter in series can also be a delay cell.

 

[incol]

If M2 and M3 have independant gate bias voltage, they are current source load. Two minimum inverter in series can also be a delay cell.

how much is the gate bias voltage, I had used a 1.22v gate bias voltage, but the output waveform is not good. This structure is better than diode connected?
and about two minimum inverter in series, I think differential structure is better than single structure.

 

[Alles Gute]

For diode connected transistor, Vds=Vth+Vd,sat
For the current source load, Vds=Vd,sat

Added after 1 minutes:

You said you need differential structure delay cell, then I think Maneatis can help you

 

[incol]

is this delay cell usefull?
M7 is a current source, M6 is source follower, so Vout1=Vds of M2.