mappycarol
Newbie level 5
parallel shielding
I have several "quiet" signals need to be shielded by ground in a mix-signal chip with UMC 6 metal process.
For better result, a designer proposed that the signals should be shielded be 4 walls-- 2 vertical metal layers running below and above , 2 parallel running along. The thickness of the metal layers is about 0.3 um and the minimum width of signals is 0.2um.
I think this way is too costly, because it'll use up 3 metal layers routing together, plus the width is less than thickness. From parasitic capacitance point of view , parallel is dominant. Does this trade-off worth it?
What do you think?
And does anybody tell me the effect of 4-wall shieding and 2-wall shielding? [/b]
I have several "quiet" signals need to be shielded by ground in a mix-signal chip with UMC 6 metal process.
For better result, a designer proposed that the signals should be shielded be 4 walls-- 2 vertical metal layers running below and above , 2 parallel running along. The thickness of the metal layers is about 0.3 um and the minimum width of signals is 0.2um.
I think this way is too costly, because it'll use up 3 metal layers routing together, plus the width is less than thickness. From parasitic capacitance point of view , parallel is dominant. Does this trade-off worth it?
What do you think?
And does anybody tell me the effect of 4-wall shieding and 2-wall shielding? [/b]