A question regarding the n-well connection of PMOS

Hi all, when I was reading Hans Camenzind's book (http://www.designinganalogchips.com/_count/designinganalogchips.pdf), I have a question at page 33. Here is what the author said
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If you place all the p-channel transistors in a common n-well, you get the smallest total area
and therefore the lowest cost. But if the source of such a transistor is operated below the positive supply, the back-gate (the n-well) pinches off the channel further and you get a reduced gain (by perhaps 30%). You can avoid this by placing this transistor in its own n-well.
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Here are my questions:
(1) why we call n-well a "back-gate"?
(2) for normal PMOS, we connect bulk with source to VCC. In this text the author mentioned, if VCC is lower than the normal value, the gain will be reduced. But the author said we can avoid this by placing the transistor in its own n-well. My question is why when a PMOS has a single n-well, its gain will not be destroyed, if its source and its n-well still connect to lower VCC.


Thank you!

The Nwell acts sort of like a JFET gate, fighting the P
inversion channel. More commonly it's referred to as
body effect and considered as a shift in VT, but the
JFET concept might be a more agreeable visualization.

It's the relation of well to source potential that the
remarks refer to. A transistor operated at (say)
VB=VS=vdd has the same VTeff as one with
VB=VS=vdd/2 - key being VB=VS.

With two transistors, same well, different VS this
cannot be the case and one must suffer.

Hi dick_freebird, thank you for your advise! From your statement I learned that we cannot have two transistors with the same Vb but different Vs. But could you use the example to explain again how to understand the last sentence of the text, "You can avoid this by placing this transistor in its own n-well"?
Assume we have two PMOMS, and their VS are connected to VCC/2, then?

dick_freebird said:

The Nwell acts sort of like a JFET gate, fighting the P
inversion channel. More commonly it's referred to as
body effect and considered as a shift in VT, but the
JFET concept might be a more agreeable visualization.

It's the relation of well to source potential that the
remarks refer to. A transistor operated at (say)
VB=VS=vdd has the same VTeff as one with
VB=VS=vdd/2 - key being VB=VS.

With two transistors, same well, different VS this
cannot be the case and one must suffer.

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