John Xu
Member level 3
hi,
I am designing a hysteresis comparator with 0.6um CMOS. The circuit is the classic topology which I refered from the book "CMOS analog circuit design"by Philip E.Allen and Douglas R.Holberg. The hysteresis of comparator is implemented by positive feedback in the input stage of a high-gain,open loop comparator. Pls. refer to the attached schematic.
In simulation, I found the hysteresis is sensitive to the mismatch of the input stage. e.g., if I set the differtial pair of input stage at 4% mismatch,the hysteresis will disapeared. It is a serious issue, beasue per my understanding, 4% mismatch is normal for CMOS process.
Can anyone give any idea to improve the mismatch issue on it?
Thanks in advance!
I am designing a hysteresis comparator with 0.6um CMOS. The circuit is the classic topology which I refered from the book "CMOS analog circuit design"by Philip E.Allen and Douglas R.Holberg. The hysteresis of comparator is implemented by positive feedback in the input stage of a high-gain,open loop comparator. Pls. refer to the attached schematic.
In simulation, I found the hysteresis is sensitive to the mismatch of the input stage. e.g., if I set the differtial pair of input stage at 4% mismatch,the hysteresis will disapeared. It is a serious issue, beasue per my understanding, 4% mismatch is normal for CMOS process.
Can anyone give any idea to improve the mismatch issue on it?
Thanks in advance!