a question on the dc offset loop

Status
Not open for further replies.

chang830

Full Member level 5
Joined
Feb 11, 2006
Messages
267
Helped
14
Reputation
28
Reaction score
3
Trophy points
1,298
Visit site
Activity points
3,425
I have a question on the dc offset loop for high gain amplifiers(such as limiting amplifiers). we know, to reduce the mismatch effect of very high gain amolifier, a dc offset loop is always included in the design. Except the low pass RC filter, I found some of them have a buffer(such as source follower)in the loop path, while some of them have a amplifier(transconductor)stage in the loop opath.

Would anyone tell me why a buffer, amp stage included in the lop path? In what conditions, a buffer, amp stage or none of them selected in the loop path?

Thanks
 


I can only guess because I can't see the schemtic of the buffer method and the transconductor method. Maybe the source follower is used as a level shifter for some particular consideration. Sometimes the Gm-Cell is used in the feedback path in order to reduce the chip area by replacing the RC integrator with Gm-C integrator.
Any way, the RC filter is the most popular method in DC offset cancellation loop and most effective.

sixth
 


Thanks for the reply!

Sorry, it caused some confuse. I mean the low pass filter is still consists of RC filter, but some also have a buffer or Gm stage in their loop path.

Can anyone explain it?

Thanks
 

Status
Not open for further replies.
Cookies are required to use this site. You must accept them to continue using the site. Learn more…