a question for back-end engineers...

[Arturi]

What factors influence the setup and hold times of Latches and flip-flops?

I know that the propagation delay of a standard gate depend on its input slew and output load. What about setup and hold for FFs? Maybe the clock slew and the output load???


cheers

 

[rjainv]

Setup time depends on slew of input data and clk.
C2Q depends on slew of clk and output load cap.

 

[shiv_emf]

setup and hold times ..... depend on transition @input and @ clock transition !!

 

[drchakravarthy]

set up and hold time constraints are based on the propagation time and settling time of the flip flop.propagation time is the time to produce a change in the output. settling time refers to the time for all the output to take a stable value

 

[sekapr]

In a master-slave type flipflop, you have two latches with passgates which are operated(opening and closing) by clock and clock-bar. When the first latch is in the transparent mode the slave latch will be in latching mode and vice versa. Simple latch will have back to back connected inverters and a passgate. So there will be a RC delay from the data port of the master latch to the point where it reaches the gate of first inverter. This RC delay plus the time the gate takes to reach 50% level is setup time.