A question aboutSCV contraints and IUS mix_simulate runtime ?
Firstly ,I have written a systemc model . I am compiling the systemc model , and inputting systemc stimulus with constraints .The simulating of the systemc model quickly completed.
Secondly ,I intend to mix_simulate the systemc model and verilg RTL code ,the stimulus inputted is also systemc stimulus with same contraints. but this time ,simulating is very slow. That is why?