Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

a question about period jitter and absolute jitter

Status
Not open for further replies.
Fractional-N

Fractional-N

Full Member level 1
Full Member level 1
Joined
Oct 15, 2007
Messages
97
Helped
2
Reputation
4
Reaction score
2
Trophy points
1,288
Activity points
2,071
it is said that "If the reference is jitter free, then the jitter between the reference and the output of the delay line will just be the period jitter."

can anyone explain to me why?
thanks
 

Since we are not on the Planet Zoltar, where signal sources are available that are "jitter free", I do not know what that statement means!
 

I believe you can think of the delay line as a series of buffers with no memory (i.e. loops), therefore jitter affects only the length of each period.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top