A very slow risetime may affect the driver. Any risetime
greater than the driver prop delay should be suspect,
and tested.
In addition to slowness you might see "multi-pulsing"
if the risetime is slow enough that ground bounce can
"wrap back around to the input" before the output moves
appreciably (as with very strong predrivers and high
internal loading, to create a leading ground impulse
before the output stage swings, perhaps causing the
front end to "dither" until the input has passed the logic
threshold plus any in-the-moment ground perturbation).
PWM resource risetimes probably are sandbagged for
external loading, and timing is probably quite "notchy"
when you get to the narrow pulse width end. You might
prefer to use a fast one-shot and a regular logic resource,
and get your pulse control some other way than a PWM
register and perhaps-too-leisurely PWM output buffer
(if that's different than a logic I/O).