A question about digital module timing constraint!

[precession]

Here is a depiction from Synopsys DC document.
But I really can not understand why "min = min_path - hold".
Let's think about the ideal case which the min_path equal to zero.
In this case, the output_delay value is negative.
Negative output_delay value means that the data could be changed unavailable before the clock’s active-edge. But how could that possible?
I can not understand. Who can explain it to me?
Thank you very much!

 

[claint]

the hold value (0.4) is the new data available time after the posedge of clock.

If this value is 0, then mim output delay is just the min path delay out of chip.
so the constrained internal path delay inside chip is -min_delay.

If the hold value is greater than zero, it requires that the data should keep stable longer time, so the min path delay inside chip is -min_delay+hold, so the min output delay is just -(-min_delay+hold)= min_delay-hold . This constraint is more strictly than that of the case with hold value 0.

 

[precession]

Ah, I see, I see.
Sorry, I made a mistake.
Output_delay is the time needed before but not after the clock's active-edge.
So negative output_delay value exactly means the hold time after the active clock edge, when the the min_path equal to zero.
So, problem solved. Who can tell me how to delete this post?