It seems I may not understand your objective.
Here is a 100mV pulse driven resonant circuit.
Notice the base is biased all the time giving continuous current and lower distortion with >2x Vcc output into a 10K load. ( based on a loaded Q.)
The input cap is just for AC coupling not diode clamping.
View attachment 120776
The difference in peak voltages of Sine out is an indication of asymmetry. from Vce saturation.
An improvement on this would have negative feedback on peak amplitude to prevent saturation or a higher impedance load.