There is no relation b/n the cache and memory of the ARM core (u r thinking of inbuilt I guess). Cache is extremly costly but with good performance. There are modren ARM cores with in-built Cache especially for network processors with StrongARM as core engine; where you have these, write through/back options will be used to handle memory. On the other hand, u can even interface memory externally/certain cores exists in built SRAM/DRAM through the address bus which will be connected to AMBA bridge inside ARM.
...abid
Thank you for your reply.
Yes, the cache I mean is build-in the arm process. Since there are no specific I/O for the arm process, everytime I write data outside of the process, like to fifo, it seems that the data will be first written to dcache, and then written out. If I try to write out the same data, I just get one from the fifo, so I think it might be the problem of cache.