fenglei
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When I was reading the datasheet,I have a question about the datasheet.
at the page 7 of the datasheet, promises a throughput rate of 117 kHz as below.
But when I calcalate the read time referring to the photo below,it turns to be (16.5 *1/8.33MHz=1.98us),for the rising edge of the SCLK should be 6us after the rising edge of convst and the final falling edge of SCLK should be 600ns prior to the next rising edge of convst.
best regards,
fenglei
at the page 7 of the datasheet, promises a throughput rate of 117 kHz as below.
But when I calcalate the read time referring to the photo below,it turns to be (16.5 *1/8.33MHz=1.98us),for the rising edge of the SCLK should be 6us after the rising edge of convst and the final falling edge of SCLK should be 600ns prior to the next rising edge of convst.
best regards,
fenglei