wizardyhnr
Junior Member level 3
I am just design a DDS and decides to use the pipeling adder to implement the phase adder of DDS. But the problem is that for a pipeling adder, it may take n clocks to get the adding result, while the adder in fact needs to result of the first adding clock to be ready when the second adding clock begins. So it is contraversive, I cannot solve it, would anyone who knows the answer do me a favor to let me know the solution for phase adder implemented with a pipeling adder. Thanks.