zhoulin999
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I want to use verilog.inpfiles.flattened from schematic which has some behavior view and has `include definition inside.
The problem is that virtuoso flatten netlisting seems to fetch contents inside `include definition instead of just leave this `include on the netlist. That causes my netlist a mess and somtimes can not be used for simulation.
Here is my my.simrc for verilog netlist generation.
The problem is that virtuoso flatten netlisting seems to fetch contents inside `include definition instead of just leave this `include on the netlist. That causes my netlist a mess and somtimes can not be used for simulation.
Here is my my.simrc for verilog netlist generation.
Code:
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; FOR HSPICE
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
simNlpGlobalLibName = "mqd2"
simNlpGlobalViewName = "hspice"
hspiceSimStopList = '("hspice")
hnlHspiceNMOSBulkNetName = "gnd"
hnlHspicePMOSBulkNetName = "vcc"
hnlHspiceNPNSubNetName = "gnd"
hnlHspicePNPSubNetName = "gnd"
; M49 options
;hspiceSimViewList = '("schema_hsA" "schema_tmp" "schema_model" "hspice" "cmos_sch_std" "cmos_sch" "schematic")
;hspiceSimViewList = '("schema_hs5" "schema_hs" "schema_hs3" "schema_hs4" "schema_hs2" "schema_hs1" "schema_model" "hspice" "cmos_sch_std" "cmos_sch" "schematic")
;L04
hspiceSimViewList = '("schema_border" "schema_border_r" "schema_fcsim" "schema_array" "schema_pmp2" "schema_model" "hspice" "cmos_sch_std" "cmos_sch" "schematic")
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; FOR VERILOG
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
hnlMaxLineLength=150
simNetlistHier= t
simReNetlistAll= t
simVerilogSimTimeUnit = "ns"
simVerilogSimTimeValue = 1
simVerilogSimPrecisionUnit = "ps"
simVerilogSimPrecisionValue = 10
;simVerilogTestFixtureTemplate = `(t "verilog")
simVerilogTestFixtureTemplate = "Verilog"
;;preserve bus
simVerilogHandleAliasPort = 'nil
simVerilogFlattenBuses = nil
simVerilogNetlistExplicit= t
;simVerilogNetlistExplicit= t
simVerilogDropPortRange = t
simVerilogIncrementalNetlistConfigList = t
vlogifUseAssignsForAlias = t
simVerilogEnableEscapeNameMapping = nil
;vlogifSkipTimingInfo = t
vlogifSkipTimingInfo = nil
;;trireg property -- from Italy
hnlVerilogITTtrireg = t
simVerilogHandleSwitchRCData = t
;; rom code netlist
;;L05A RTL
verilogSimViewList = '( "schematic_empty" "functional" "behavioral" "behavioral_rom" "behavioral_sram" "logic_q" "logic" "schematic_ver" "schematic_blk" "optB_sch" "optA_sch" "ann" "verilog" "schematic" "cmos.sch" "cmos_sch" "hspice" )
verilogSimStopList = '( "functional" "behavioral" "behavioral_rom" "behavioral_sram" "pnr" "verilog" "symbol" "ann" )
;;L05A gate
;;verilogSimViewList = '( "behavioral" "behavioral_rom" "behavioral_sram" "logic_q" "logic" "schematic_blk" "optB_sch" "optA_sch" "ann" "verilog" "schematic" "cmos.sch" "cmos_sch" "hspice" )
;;verilogSimStopList = '( "behavioral" "behavioral_rom" "behavioral_sram" "pnr" "verilog" "symbol" "ann" )
;;L05A rom_top
;;verilogSimViewList = '( "optB_sch" "optA_sch" "ann" "verilog" "schematic" "cmos.sch" "cmos_sch" "hspice" )
;;verilogSimStopList = '( "pnr" "verilog" "symbol" "ann" )
;add by Cindy: change WARNING (OSSHNL-259) to ERROR
simCheckTermMismatchAction="error"
simVerilogGndNetList = '("Vss!" "VSS!")
simVerilogGndNetList = '("gnd!" "GND!" "vss!")
simVerilogPwrNetList = '("Vdd!" "vdd!" "VDD!" "vcc!" "Vcc!" "VccE!" "vccp!")
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; FOR VERILOG
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;simVerilogDropPortRange = nil
;simVerilogGndNetList = '("gnd!" "GND!" "vss!")
;simVerilogNetlistExplicit= nil
;simVerilogPwrNetList = '("vdd!" "VDD!" "vcc!" "Vcc!" "VccE!")
;simVerilogSaveWaveformOption = "saveall"; or "probes" or "primaryio"
;simVerilogTopLevelModuleName= "ts.f"
;verilogSimBinary = "/var/cds/tools/verilog/bin/verilog"
;verilogSimStopList = '("ann" "functional" "behavioral" "verilog")
;vlogifCurrentTestFixture = "testfixture.template" ; undocumented in openbook
;simVerilogTestFixtureTemplate = "Verilog" ; no veritime or verifault templates produced.
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; FOR POWERMILL
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
hnlTmCapParamList ='("c" "cr" "m")
hnlTmFloatCapacitor = t
hnlTmModelParamList = '("pwa" "pwo" "nwa" "nwo" "nl" "nw" "pl" "pw" "w" "l" "M" "m" "sc" "rr" "cr" "lr" "wr")
hnlTmNmosParamList ='( "w" "l" "m")
hnlTmNoPortMap = t
hnlTmPmosParamList ='( "w" "l" "m")
hnlTmResistorParamList='("r" "rr" "m")
simTmGndNetList = "gnd!"
simTmVddNetList = "vcc!"
timemillSimStopList ='("timemill")
hnlSupportIterInst = t
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