a problem about output matching of LNA

[tiger_ads]

lna output matching

i have read the topic "lna &mixer test design in receiver" ,I understand a lot, but still have some confuse.

i am going to design a lna and a mixer individually on the same chip,so dont i need a buffer??
i want to know the details about output matching of lna, as i have read, the output is high Q node, so it is hard to match it on chip, this meaning is matching is on board?? when simulationg, use ideal passitive component is for this reason??
and what simulation result should i concern about when output matching?? only S22??
my lna is single end with two stage, one is cascode, the other is common source for improving gain. what should i do for output matching???
thanks a lot !!

 

[khouly]

kf stability cadence

if u mean matching circuits between onchip LNA and mixer u donot need it

but if u want to match the LNA to the 50 ohm u will a high qualtiy matching circuit
u can make on board , by using microstrip lines or lumped elements


wish this help

khouly

 

[tiger_ads]

yes, i need match the lna to 50 ohms. i have swept the L and C values simultaneously, and in smith chart it can be matched in centre, but when i sweep frequence, the result is not correct. i think it may be oscillated, i want to know how to simulate the stability?? how can i improve it?? add a capacitor between gate and drain??

thanks

Added after 4 minutes:

i simulate this LNA using cadence SpectreRF, could you explain in detail??

 

[dsjomo]

yes, i need match the lna to 50 ohms. i have swept the L and C values simultaneously, and in smith chart it can be matched in centre, but when i sweep frequence, the result is not correct. i think it may be oscillated, i want to know how to simulate the stability?? how can i improve it?? add a capacitor between gate and drain??

thanks

Added after 4 minutes:

i simulate this LNA using cadence SpectreRF, could you explain in detail??

Adding a cap. between Gate and Drain to improve stability?? Man, you are suiciding.

I remember there is a "Kf" on SpectreRF's sparam simulation. That is the stability factor you should check first.

 

[SkyHigh]

There are several ways:

1. Use HP-ADS, import your circuit. You can use L, T or Pi matching filter and add it to the output of LNA (drain). Let the HP-ADS generate the Smith Chart for you and all you need to do is to adjust the values of C and L and check the Smith Chart to see if you are getting what you want. Sometimes C or L tapped matching filters are used.

2. Another way is the hand calculation method. If you know the gm, rs, etc, generate a small-signal model of your LNA, place a pull-up inductor to drain, capacitor (one end to drain and the other end to 50-ohm shunt to ground) and derive the model. Calculate the values you need for C and L.

You want more information, read Razavi - "RF Microelectronics" or Thomas H Lee - "RF Integrated Circuits"

 

[tiger_ads]

to dsjomo
why do you speak so?? adding a cap between gate and drain is unvailable?? i have read a paper who suggest it, could you explain it?
i have read "Kf" , it<1, and Zout is negative,so this is not unconditional stable , how can i improve it?? add a resister at the output??
thanks!!

to skyhigh
i am just doing it as your second method, at the output of second stage adding a pull-up inductor, adding a cap with one terminal at the drain,the other at the 50ohms port. my problem is the circuit is unstable now! when i sweep the L and C, S22 is less than unity, but when i sweep the frequence, the result is not same. and the Zout is negative.
thanks

 

[dsjomo]

to dsjomo
why do you speak so?? adding a cap between gate and drain is unvailable?? i have read a paper who suggest it, could you explain it?
i have read "Kf" , it<1, and Zout is negative,so this is not unconditional stable , how can i improve it?? add a resister at the output??
thanks!!

Can you give me a direction where can i find the paper you mentioned above? thx!

If you want a intuitive explaination of why its harmful to put a cap. at that place, think as follow:
A cap. between Port 1 and Port 2 means a capacitive signal path. So enlarge the cap also enlarge S12. If all the other S-params are fixed and we rise S12, that means K tends to be less than 1 more easily.
Everything that tends to increase S12 should be forbidden as a rule of thumb, except resistive feedbacked broad band LNA.

Your circuit is an oscillator, if any part of Zout or Zin is negetive.

If you want a simple solution to solve the problem.
(1) yes, a resistor at output
(2) source inductive degeneration

 

[tiger_ads]

but how the resistor is connected? shunt or series?? what value? is there a rule which can be followed?? thanks
i try to add it ,one terminal is connected to cap which is used for matching,another is connected to 50ohms output, is it correct?

 

[tiger_ads]

when i add a resistor in series at output , "Kf" is improved, but S11 is deteriorated, Zin is less than 50 ohms, what should i do? S22 is approximately -4dB, is it reasonable??

thanks

 

[dsjomo]

but how the resistor is connected? shunt or series?? what value? is there a rule which can be followed?? thanks
i try to add it ,one terminal is connected to cap which is used for matching,another is connected to 50ohms output, is it correct?

Normally, one of the node of the loading spiral has the highest voltage in the whole circuit (the other node of the spiral is connected to VDD). So we have to prevent this voltage signal leakaging to input port. A traditional strategy is placing a small resistance between this node and the collector of transistor, I guess this is whay you call SERIES.

You can place a resistor SHUNT to the spiral to attenuate the node voltage in the similar manner. I guess this is what you call SHUNT.

Both of them should work.

The funniest thing is that, while everyone trys to enalrge the Q of spiral inductor, we put a resistor paralleling the spiral inductor for stability. So, for LNA design for general telecom, we don't need a ultra high Q spiral. While VCO needs ultra high Q spirals for phase noise.

 

[tiger_ads]

i am very very sorry, i can't understand your meanings exactly because of my poor english and lack of knowledge of RF circiut.
i have attached my schematic followed by Thomas Lee. now i need to match output to 50 ohms and guarantee its stability. how should i do??
the drain of 2nd stage is connected a L and C used for matching, where the resistor should insert??
thanks !!!!

 

[tiger_ads]

hi djsomo
i have simulated the circuit, the shematic(have added the resistor at the output) and simulating results have been attached. could you examine them, then suggest me to ajust parameter. thanks!!
are these curves correct??
the IIP3=-13.4285dBm, how can i improve it??
when plot the 1-dB compression poin and IIP3, setting the extrapolation point differently ,the result is different. how should i set this parameter??


i am a beginner in RF, having a lot of experience need to learn, sincerely hoping you can criticize me, i would try my best to improve myself! thanks again

 

[dsjomo]

hi djsomo
i have simulated the circuit, the shematic(have added the resistor at the output) and simulating results have been attached. could you examine them, then suggest me to ajust parameter. thanks!!
are these curves correct??
the IIP3=-13.4285dBm, how can i improve it??
when plot the 1-dB compression poin and IIP3, setting the extrapolation point differently ,the result is different. how should i set this parameter??


i am a beginner in RF, having a lot of experience need to learn, sincerely hoping you can criticize me, i would try my best to improve myself! thanks again

I have some comments and advice for you,

(1) S-params, they looks correct from 1GHz to 3GHz. But, the schematic of your circuit is only a core circuit of LNA, it does not includes the parasites of bondwires, pads, package and PCB. So the simulation resulte might be very different after adding those parasitic effects. For a single-end LNA operating at 2.4GHz, you don't need to put a spiral inductor for source degeneration, because usually, the bondwire inductance is enough.

You have to put bondwire model to sim. LNA, at least.

(2) NF and Kf, since you chose 0.35um process, a NFmin between 2~3dB is acceptable. And, remember that, Kf should be greater than one, so you'd better redraw you Kf curve and modify your setting of Y-axis to draw from 0 to 5. And, the most common problem of oscillation is due to the parasites on PCB at several hundred MHz to GHz. So the range of X-axis should be set larger.

You have to put every parasitic model to simulate, otherwise all you do is GIGO(Garbage In Garbage Out).

(3) The resistance for stabilization could be work, but traditionally, cout should be attached to the common node of rout and lout.

(4) Don't put the current refference resistance on-chip.

 

[tiger_ads]

This is my first design, even don't know how to get these parameters?? who i should ask for these parameters? foundry? or others?
should source inductor be replaced by ideal one while simulation??
this design is for lab,so there is no packaging, at least i think so. my boss is expert on optic transceiver, knowing little on this area, but he would like to set food in this area, so i am the victim, but i am very interested in it!! there are a lot of simulation resources in our school, Cadence ,ADS, soon will buy RFDE, but lack of test instrument and experience seriously!!

Added after 1 hours 25 minutes:

hi djsomo
i have added the cout to the common node of rout and lout, the S22 could be easily adjusted below -20dB, but the S11 always be around -10dB, S11 and S22 could not be set well simultaneously! in other words, this change affect input port seriously! why?? i have to make this change??? by the way, rout should be on chip or off chip??

as you said, current refference resistor is the one added to the drain of bias MOS??

i have checked "Kf" , it always more than unity before making change

the attachment is the schematic and the result after making change

thanks

 

[tiger_ads]

i have done it followed by your suggestion, cout is connected to the common node of rout and lout, "Kf" is always more than unity.

now, could you explain how to consider parasitical facts? give me a direction! thanks!!

 

[dsjomo]

i have done it followed by your suggestion, cout is connected to the common node of rout and lout, "Kf" is always more than unity.

now, could you explain how to consider parasitical facts? give me a direction! thanks!!

You can run Calibre-XRC to extract parasitic R and C. So you have to design your chip layout first. Then extract the layout with XRC.

For pad parasites, run EM simulator or send a pad test key in the pre-design run to extract the parasites by measurement results.

How large is the bias current of your 2nd stage?

 

[charliefan]

I think you should concern more in K,NF,Gain,and do not pay so much attention to S.

 

[tiger_ads]

first of all, i should draw the layout, then extract the parasities including R ,C,
pad, and bondwire parasities?? i heard of Cadence can run package simulation,but i haven't used it!

the bias current of 1st stage is 6mA, the 2nd stage is used to improve the Gain,i don't care about it ,so i must check it first ,then tell you

thanks

Added after 4 minutes:

to charliefan
could you explain it in detail? i think if the imaginary parts of S11 is bad, showing the imaginary matching of noise is also bad, is it correct??

thanks

 

[dsjomo]

first of all, i should draw the layout, then extract the parasities including R ,C,
pad, and bondwire parasities?? i heard of Cadence can run package simulation,but i haven't used it!

the bias current of 1st stage is 6mA, the 2nd stage is used to improve the Gain,i don't care about it ,so i must check it first ,then tell you

thanks

Yes, you are right.

There is a nice package modeler in Cadence Environment, it is a simple but convenient program. But it can't generate QFN package model.

 

[tiger_ads]

now i can draw the layout as the schematic completely???
don't i need to add some components to simulate the parasitical effect??
thanks!!