a problem about divided by two circuit!

[kolarbear]

www.comercialdividers.com

Hi, everyone!
I tested a CML divided by two circuit, but met some problem.
The minimum input power of my circuit is around 0dBm, which is different from my simulation result of -10dBm. I think it is caused by oscillation. When it has no input power, the divider outputs a frequency around 20GHz with the power around -35dBm. The DC voltage of my output pad is different from my simulation result when there is no RF input, but when the circuit works, the DC voltage is right.

I'm confused about the problem. How can I cancel the oscillation?

 

[kolarbear]

Anyone give me some suggestions?

 

[krashkealoha]

From what you have described, the oscillation you are seeing is the self-oscillation of your divide by 2 circuit. This self-oscillation point is normal for all dividers once you go below it's input sensitivity.

To figure out why you are not meeting the -10dBm could be losses due to your pcb traces, metal interconnect on the chip, etc.

 

[biff44]

It USED to be a problem in dividers:

www.cel.com/pdf/appnotes/an1014.pdf

But I am not aware of any modern comercial dividers that self oscillate.

 

[rfsystem]

Commercial could mean more user friendly but possible more power consuming.

That is because the highest sensitivity and lowest power is where the divider operate as injection locked oscillator. I think you have the lowest required power level for correct operation where the selfoscillation is.

If selfoscillation should be blocked you simply have to make a small mismatch in the diffamp stages. That is the commercial trick.

But for selftesting the divider chain this kind of selfoscillation is used many time. So you disable the VCO and test the divider chain with a technology matched signal frequency.

 

[kolarbear]

But any other reasons except losses due to your pcb traces, metal interconnect on the chip, etc?

Because my losses seem not to be so large.

 

[krashkealoha]

Because my losses seem not to be so large.

What did you do to verify this? What is the input frequency of this divider?

Other things to look at:
1) Did you extract the parasitics from the layout and include them in your simulation?
2) If the part is packaged, did you include a package model in your simulation?
3) If this is a bipolar technology make sure you are not saturating any transistors, because simulation doesn't simulate these effects that well.
4) Are the measured transistor parameters representative of the models that you simulated with?