a problem about CML frequency divider

[will_tp]

cml divider

I use CML divider to generate quadrature signal.
Should the input clock to CML be fully differential?
A group of digital divider outputs "clk" and "clkb" just is inverse of "clk".
If using "clk" and "clkb" as CML input, what problem will be have?

 

[mikersia]

in high speed design a well ballanced differential signal is used. Generation of differential clock by using additional inverter (with pure controllable PVT delay) will increase jitter and limit maximum operation frequency