a pipeline ADC with 100M sps/s ,8 bits design

[mickywang]

hello everyone:

I want to design a pipeline ADC of IC with 100M sps/s 8 bits resolution ,hope everyone give me some
experience and papers about pipeline ADC, as well as configure of circuit.

best regards
micky

 

[shiowjyh]

Some reference might be helpful to you...

1. Jun Ming, Stephen H. Lewis;
An 8-bit 80-Msample/s pipelined analog-to-digital converter with background calibration,
IEEE Journal of Solid-State Circuits, vol. 36, pp. 1489 - 1497, October 2001.

2. Lauri Sumanen, Mikko Waltari, Kari A. I. Halonen;
A 10-bit 200-MS/s CMOS parallel pipeline A/D converter,
IEEE Journal of Solid-State Circuits, vol. 36, pp. 1048 - 1055, July 2001.

3. Myung-Jun Choe, Bang-Sup Song, Kantilal Bacrania;
An 8-b 100-MSample/s CMOS pipelined folding ADC,
IEEE Journal of Solid-State Circuits, vol. 36, pp. 184 - 194, February 2001.

4. Ion E. Opris, Bill C. Wong, Sing W. Chin;
A pipeline A/D converter architecture with low DNL,
IEEE Journal of Solid-State Circuits, vol. 35, pp. 281 - 285, February 2000.

5. Paul C. Yu, Hae-Seung Lee;
A 2.5-V, 12-b, 5-Msample/s pipeline CMOS ADC,
IEEE Journal of Solid-State Circuits, vol. 31, pp. 1854 - 1861, December 1996.

6. Thomas Byunghak Cho, Paul R. Gray;
A 10 b, 20 Msample/s, 35 mW pipeline A/D converter,
IEEE Journal of Solid-State Circuits, vol. 30, pp. 166 - 172, March 1995.

7. Iuri Mehr, Larry Singer;
A 55-mW, 10-bit, 40-Msample/s Nyquist-rate CMOS ADC,
IEEE Journal of Solid-State Circuits, vol. 35, pp. 318 - 325, March 2000.

8. K. Nagaraj, H. S. Fetterman, J. Anidjar, S. H. Lewis, R. G. Renninger;
A 250-mW, 8-b, 52-Msamples/s parallel-pipelined A/D converter with reduced number of amplifiers,
IEEE Journal of Solid-State Circuits, vol. 32, pp. 312 - 320, March 1997.

and see more on IEEEs....

Regards,