A net is not a legal lvalue in this context!! Help

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Harishddixit

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Hi All ,

Obtaining the following error when compiling the code mentioned below the error :

Error :




Code Verilog - [expand]
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module checker( output logic Clock, Reset, Enable,UpDn , output reg Load, input reg [7:0] Data , input reg [7:0] Q );
          
     reg [7:0]temp;
     assign Q = (temp);
         
    initial
    begin
    Clock = 0;
        forever #10 Clock = ~Clock;
        #1000 $finish;
    end
 
    initial
   begin
    temp=0;
   end
 
    always @ (posedge Clock)
  begin         
        Reset=1;
        #10 Reset=0;
        Enable=1;
        Load=$urandom;
        UpDn=1;
        Data=$random;
    
    
 end
endmodule


Please help how to fix the issue, Beginner here
 
Last edited by a moderator:

You have Data as an input, and are trying to assign something to it.
 

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