A Lot of Questions on Power Factor Correction Circuit

[simbaliya]

I am a master student currently doing a project aiming at designing a power factor correction circuit with better performance(eg: higher PF, or higher power efficiency, etc). For me this is an new area, everything seems not familiar to me, so I spent a couple of days to learn from the fundamental knowledge of PFC to datasheet of real designs. Now the problem is that I am the only guy doing PFC in school and I have a lot of doubts which can not be discussed with or answered by anybody around me. I am now posting my questions here, hoping some of you good guys can help me on these.

Q1. Except for power loss from conduction of diode and switch(ignore the I2R loss of wire), what are the rest power loss in PFC converter with boost topology?

Q2. Since we can use flyback topology to implement PFC, which means the output can be lower than the input, does that mean if we use this design, the followed DC-DC converter is not needed any more?

Q3. How to determine whether the PFC works in CCM or DCM mode? I know in CCM the inductor current never goes to zero at the beginning of ON time and at the end of off time, while in DCM it goes to zero, but how to implement the current goes or does not go to zero in the circuit?

Q4. In the voltage loop, the Vo and the Vref are fed into a block called PI regulator, is that a simple substractor? or something else? Please give me some details about this block.

Q5. What are all the possible specs that can be improved in PFC design?

 

[mtwieg]

Q1. Except for power loss from conduction of diode and switch(ignore the I2R loss of wire), what are the rest power loss in PFC converter with boost topology?

Switching losses in the switches and diodes are often a contributor to losses. At high switch frequencies, they can easily dominate all other loss terms.

Q2. Since we can use flyback topology to implement PFC, which means the output can be lower than the input, does that mean if we use this design, the followed DC-DC converter is not needed any more?

Not necessarily. One thing inherent to all PFC front end converters is that they have very low bandwidth in their voltage control loop. Such low bandwidth is necessary to get a good PF. But such a low bandwidth on the output may not be acceptable, even if it is at the right voltage. So often another regulator with higher bandwidth is used after the PFC. Another thing, the output capacitor bank of a PFC will have significant ripple at twice the line frequency, which may not be acceptable to the load.

Q3. How to determine whether the PFC works in CCM or DCM mode? I know in CCM the inductor current never goes to zero at the beginning of ON time and at the end of off time, while in DCM it goes to zero, but how to implement the current goes or does not go to zero in the circuit?

This is a design issue that depends on a lot of things, and can be a complicated choice. CCM will give higher efficiency at high power levels, and lends itself to average current mode control (ACMC). DCM is nice at low power levels, especially with flyback converters, since all of your stored energy in the flyback is delivered to the load every cycle. However the control scheme is trickier, I think, since peak current is proportional to average current squared in instead of being proportional to average current.

Q4. In the voltage loop, the Vo and the Vref are fed into a block called PI regulator, is that a simple substractor? or something else? Please give me some details about this block.

It can be a lot of things, but normally it's more than a subtractor (difference amplifier). PI means proportional+integral controller. Loop up PID controllers on wikipedia for more info. It doesn't have to take that form, but it's usually something comparable.

Do you plan on controlling this thing with a microcontroller, or with an off the shelf control IC, or with your own analog electronics?

Q5. What are all the possible specs that can be improved in PFC design?

Well, you're probably not going to break any records. People have gotten efficiencies over 99%, power densities over 100W/inch^3, and line distortions down to -60dB. All pretty incredible. It's a very well researched topic, which makes it hard to fine a niche in... most of the research I've come across is about very exotic topologies (mostly useless in applications), integrated magnetics (cool, useful, but maybe not what you're looking for), or novel control schemes (often using powerful processors). Most power electronics research is like that...

 

[simbaliya]

Not necessarily. One thing inherent to all PFC front end converters is that they have very low bandwidth in their voltage control loop. Such low bandwidth is necessary to get a good PF. But such a low bandwidth on the output may not be acceptable, even if it is at the right voltage. So often another regulator with higher bandwidth is used after the PFC. Another thing, the output capacitor bank of a PFC will have significant ripple at twice the line frequency, which may not be acceptable to the load.

The output is a DC signal, why it needs a high bandwidth?

It can be a lot of things, but normally it's more than a subtractor (difference amplifier). PI means proportional+integral controller. Loop up PID controllers on wikipedia for more info. It doesn't have to take that form, but it's usually something comparable.

Do you plan on controlling this thing with a microcontroller, or with an off the shelf control IC, or with your own analog electronics?

I can only design this block in Candence environment, that's why I need to know the mechanism inside it? Like how much is the gain needed.

 

[mtwieg]

The output is a DC signal, why it needs a high bandwidth?

So that it can respond quickly the changes in the load. How much bandwidth depends on the load, but sometimes in needs to have settling times under 1ms, which is impossible for a PFC.

I can only design this block in Candence environment, that's why I need to know the mechanism inside it? Like how much is the gain needed.

The voltage loop feedback has two main purposes: to make sure the output voltage is stable, and to help define the second harmonic distortion of the input current (for single phase bridged PFC). Its specific design depends on several things, including the properties of the inner current control loop, so you should try doing that first.

 

[simbaliya]

Just read this from somewhere

In critical mode, the bandwidth of the feedback loop should be set below 20Hz to maintain a constant on-time for a line half-cycle

I can relate the bandwidth with the ability to maintain constant on time, can someone explain it to me? I think I lack the basic knowledge here

 

[mtwieg]

Just read this from somewhere

I can relate the bandwidth with the ability to maintain constant on time, can someone explain it to me? I think I lack the basic knowledge here

In a PFC the input current should always track the input voltage, and nothing else. The current reference (multiplier output) signal should be ideally modulated by the input voltage, but it is also modulated by the output voltage error amplifier. You want the signal from the voltage error amp to be much slower than the input voltage waveform, so that during each line half-cycle, the multiplier output will only track the input voltage. Setting your voltage loop bandwidth low (much lower than the line frequency) will enforce this. In reality, there will be some ripple on the voltage error signal, usually at twice the line frequency, which leads to third harmonic distortion in the input current.