[SOLVED] A lil probelm in instantation

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humairalis

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i am working on AES 32 bit
just implementing the vector part for LUT saving
can you please help me out with this

module AES(In, clk, reset, Key, Out);

input [127:0] In;
input clk,reset;
input [127:0] Key;
output reg [127:0] Out;
reg [4:0] i;
initial
begin
if (reset)
begin
for (i=0;i<=3;i=i+1)
AddRoundKey ark(In[i*32+:32], clk, Key[i*32+:32], Out[i*32+:32]);
end
else;
end
endmodule




module AddRoundKey(In, clk, Key, Out, reset);

input [32:0] In;
input clk,reset;
input [32:0] Key;
output reg [32:0] Out;
always@(posedge clk)
begin
if (reset)
begin
Out=32'h0000;
Out = In ^ Key;
end
else;
end
endmodule


i want to instantiate this module 10 times as aes have 10 rounds
pls help !
 

Instantiation is not allowed in sequential area except checker instantiation

this error i got when i synthesize
 

Forget about using "for (i=0;i<=3;i=i+1)" the way you are doing right now. Doesn't work like that. If that error is for your originally posted code, then use generate statement as suggested. If you have new code giving you this error, then please post that new code.
 

trying to learn the genvar logic
can u post it for my code.pls !

- - - Updated - - -

now it is synthesizable but output is xx.....


module AES(In, clk, reset, Key, Out);

input [127:0] In;
input clk,reset;
input [127:0] Key;
output [127:0] Out;


genvar i;
generate
for (i=0;i<=3;i=i+1)
AddRoundKey ark(In[i*32+:32], clk, Key[i*32+:32], Out[i*32+:32]);
endgenerate

endmodule




module AddRoundKey(In, clk, Key, Out, reset);

input [32:0] In;
input clk,reset;
input [32:0] Key;
output reg [32:0] Out;
always@(posedge clk)
begin
if (reset)
begin
Out=32'h0000;
Out = In ^ Key;
end
else;
end
endmodule

- - - Updated - - -

WARNING: For instance uut/\[2].ark /, width 33 of formal port Out is not equal to width 31 of actual.
WARNING: For instance uut/\[3].ark /, width 33 of formal port In is not equal to width 31 of actual.
WARNING: For instance uut/\[3].ark /, width 33 of formal port Key is not equal to width 31 of actual.
WARNING: For instance uut/\[3].ark /, width 33 of formal port Out is not equal to width 31 of actual.
Time resolution is 1 ps

now this error on test bench!

- - - Updated - - -

here is the test bench !

module ww;

// Inputs
reg [127:0] In;
reg clk;
reg reset;
reg [127:0] Key;

// Outputs
wire [127:0] Out01;

// Instantiate the Unit Under Test (UUT)
AES uut (
.In(In),
.clk(clk),
.reset(reset),
.Key(Key),
.Out01(Out01)
);
initial
clk=1'b0;
always
#1 clk=~clk;
initial begin
// Initialize Inputs
In = 32'h00000000;
clk = 1'b1;
reset = 1'b1;
Key = 32'h11111111;

// Wait 100 ns for global reset to finish
#1 reset=1'b0;
end
endmodule

- - - Updated - - -

mr fibble you are a genious

thankssss alooottt
 

humairalis said:
mr fibble you are a genious

thankssss alooottt
Click to expand...

One of the perks of being a hand puppet with glowing red eyes. ;-) Anyways, glad you got it working now.


Incidentally, did you fix the "WARNING: For instance uut/\[2].ark /, width 33 of formal port Out is not equal to width 31 of actual." warning? That sometimes is an indication that you might accidentally be using the wrong bit width. Which will then result in it working for a limited testbench, but then breaking bad in some cases.

Yeah, reading your code a bit more ... You have things like "input [32:0] In;" ... but then later on you assign In = 32'h00000000; ...

[32:0] gets you a 33 bit word. If you want a 32-bit word you want to use "input [31:0] In;" etc. So you may want to go over your code and see if everything is really 32 bits wide where you think it is...
 


again i am stuck in an issue
i dont know why the Line 74: Index <159> is out of range [127:0] for signal <Out01>.
pls helpp ! just the final task to achieve



module AES(In, clk, reset, Key, Out32);

input [127:0] In;
input clk,reset;
input [127:0] Key;
output [127:0] Out32;
reg [127:0] Key1= 128'hd6aa74fdd2af72fadaa678f1d6ab76fe;
reg [127:0] Key2= 128'hb692cf0b643dbdf1be9bc5006830b3fe;
reg [127:0] Key3= 128'hb6ff744ed2c2c9bf6c590cbf0469bf41;
reg [127:0] Key4= 128'h47f7f7bc95353e03f96c32bcfd058dfd;
reg [127:0] Key5= 128'h3caaa3e8a99f9deb50f3af57adf622aa;
reg [127:0] Key6= 128'h5e390f7df7a69296a7553dc10aa31f6b;
reg [127:0] Key7= 128'h14f9701ae35fe28c440adf4d4ea9c026;
reg [127:0] Key8= 128'h47438735a41c65b9e016baf4aebf7ad2;
reg [127:0] Key9= 128'h549932d1f08557681093ed9cbe2c974e;
reg [127:0] Key10= 128'h13111d7fe3944a17f307a78b4d2b30c5;
wire [127:0] Out01, Out11, Out21, Out31;
wire [127:0] Out02, Out12, Out22, Out32;
wire [127:0] Out03, Out13, Out23, Out33;
wire [127:0] Out04;
wire [127:0] Out14;
wire [127:0] Out24;
wire [127:0] Out34;
wire [127:0] Out05;
wire [127:0] Out15;
wire [127:0] Out25;
wire [127:0] Out35;
wire [127:0] Out06;
wire [127:0] Out16;
wire [127:0] Out26;
wire [127:0] Out36;
wire [127:0] Out07;
wire [127:0] Out17;
wire [127:0] Out27;
wire [127:0] Out37;
wire [127:0] Out08;
wire [127:0] Out18;
wire [127:0] Out28;
wire [127:0] Out38;
wire [127:0] Out09;
wire [127:0] Out19;
wire [127:0] Out29;
wire [127:0] Out39;
wire [127:0] Out010;
wire [127:0] Out110;
wire [127:0] Out210;

genvar i;
generate
for (i=0;i<=3;i=i+1)


AddRoundKey ark(In[i*32+:32], clk, Key[i*32+:32], Out01[i*32+:32], reset);
ShiftRow sr1(Out01[i*32+:32], clk, Out32[i*32+:32], reset);

endgenerate

endmodule

module AddRoundKey(In, clk, Key, Out, reset);

input [31:0] In;
input clk,reset;
input [31:0] Key;
output reg [31:0] Out;
always@(posedge clk)
begin
if (reset)
begin
Out=32'h00000000;
Out = In[31:0] ^ Key[31:0];
end
else;
end
endmodule


module ShiftRow(In, clk, Out,reset);

input [127:0] In;
input clk,reset;
output reg [127:0] Out;
always@(posedge clk)
begin
if (reset)
begin
Out=128'd0;

Out[127-:8] = In[127-:8];
Out[119-:8] = In[87-:8];
Out[111-:8] = In[47-:8];
Out[103-:8] = In[7-:8];
Out[95-:8] = In[95-:8];
Out[87-:8] = In[55-:8];
Out[79-:8] = In[15-:8];
Out[71-:8] = In[103-:8];
Out[63-:8] = In[63-:8];
Out[55-:8] = In[23-:8];
Out[47-:8] = In[111-:8];
Out[39-:8] = In[71-:8];

Out[31-:8] = In[31-:8];
Out[23-:8] = In[119-:8];
Out[15-:8] = In[79-:8];
Out[7-:8] = In[39-:8];

end
end
endmodule
 

Could you use CODE or SYNTAX tags when posting code? Makes it a bit more readable. Also, can you tell me what line 74 is, so I don't have to assume that the first line of your snippet here is actually the first line in the file.
 

ShiftRow sr1(Out01[i*32+:32], clk, Out32[i*32+:32], reset);
this line is the 74th one

dont know why i am getting out of range 159 index
however i = max 3 and if i multiply 3*32+32 so max of 127 should be there
 

How about this ...

Code Verilog - [expand]
1
2
3
4
5
6
7

genvar i;
generate
    for (i=0;i<=3;i=i+1) begin
        AddRoundKey ark(In[i*32+:32], clk, Key[i*32+:32], Out01[i*32+:32], reset);
        ShiftRow sr1(Out01[i*32+:32], clk, Out32[i*32+:32], reset);
    end
endgenerate


I think you may have forgotten to use a begin and end around the 2 module instantiations. What probably happens is this:

- no begin/end, so the for loop will be a one-liner (the AddRoundKey line).
- synthesizer finishes handling the for loop.
- when it exits the for loop the i variable will be i=4
- AFTER that completes it will now handle the line with ShiftRow, but for a value of i=4
- i=4 will result in that upper index of 159
- hilarity ensues

- - - Updated - - -

humairalis said:
ShiftRow sr1(Out01[i*32+:32], clk, Out32[i*32+:32], reset);
this line is the 74th one

dont know why i am getting out of range 159 index
however i = max 3 and if i multiply 3*32+32 so max of 127 should be there
Click to expand...

You just think i is max 3. But I will admit this one is a bit sneaky.
 
Last edited:


Incidentally, this is a good example of why you want to program defensively. Assume you will make silly mistakes like this again (I know I do if I don't watch it), and get in the habit of adding begin/end around a block. Even if currently you have only one line. If there is a reasonable chance that in the future you are going to add more code to a block that is currently just one line ... add a begin + end around it. I know that some people might disagree, and it is a matter of taste / coding style. Also don't do it everywhere, just more than you're doing right now. That saves you some time. Because right now the index is a big enough hint, but sometimes you will get no error at all, and it will happily synthesize something that is different than what you intended... And those are the mistakes that can take up some time before you find them.
 

one last question i wanted to add delay in this
like i have to run these 2 instantiated module for 10 times
and i want that round number 2 should wait for the result of round1 as round1 out is In for round 2 so where should i add the delay
 

If you want the delay to be in real hardware (as opposed to just simulation), then you will have to use a counter or something like it.

If the delay is ONLY IN SIMULATION then you can use something like #1234 to delay 1234 time-units. But do keep in mind that delays done with # are only useful in simulation. This does NOT synthesize to anything in hardware.

See this for an example on delays, to be used in testbenches: https://www.asic-world.com/verilog/vbehave4.html
 



one thing more
module SubByte(In, clk, Out,reset);

input [31:0] In;
input clk,reset;
output [31:0] Out;

SubB sb1(In[7-:8], In[15-:8], clk, Out[7-:8], Out[15-:8]);
SubB sb2(In[23-:8], In[31-:8], clk, Out[23-:8], Out[31-:8]);

endmodule

module SubB(Inbyte1, Inbyte2, clk, Outbyte1, Outbyte2);

input [7:0] Inbyte1;
input [7:0] Inbyte2;
input clk;
output [7:0] Outbyte1;
output [7:0] Outbyte2;


Sbox m1(
.addra(Inbyte1), // Bus [7 : 0]
.addrb(Inbyte2), // Bus [7 : 0]
.clka(clk),
.clkb(clk),
.douta(Outbyte1), // Bus [7 : 0]
.doutb(Outbyte2)); // Bus [7 : 0]

endmodule

module ShiftRow(In, clk, Out,reset);

input [127:0] In;
input clk,reset;
output reg [127:0] Out;
always@(posedge clk)
begin
if (reset)
begin
Out=128'd0;

Out[127-:8] = In[127-:8];
Out[119-:8] = In[87-:8];
Out[111-:8] = In[47-:8];
Out[103-:8] = In[7-:8];
Out[95-:8] = In[95-:8];
Out[87-:8] = In[55-:8];
Out[79-:8] = In[15-:8];
Out[71-:8] = In[103-:8];
Out[63-:8] = In[63-:8];
Out[55-:8] = In[23-:8];
Out[47-:8] = In[111-:8];
Out[39-:8] = In[71-:8];

Out[31-:8] = In[31-:8];
Out[23-:8] = In[119-:8];
Out[15-:8] = In[79-:8];
Out[7-:8] = In[39-:8];

end
end
endmodule

the module subbyte is basically fetching a data from block ram in 32 byte manner
but shiftrow module is designed that it has to be dealt with 128 byte all in one
so hw=ow can i made to fetch 32 byte chunks to shift row
 

I take it you are summarizing... Or is there a question in there somewhere?
 

the module subbyte is basically fetching a data from block ram in 32 byte manner
but shiftrow module is designed that it has to be dealt with 128 byte all in one
so hw=ow can i made to fetch 32 byte chunks to shift row
 

mrflibble said:
So do 4 fetch actions to get all the 128 bytes?
Click to expand...

for example here i delcare a 128 bit reg with value of 128'h
but if i try fetching it in 32 bit in 4 fetches it doesnt give the accurate output



module AES(In, clk, reset, Key, Out32);

input [127:0] In;
input clk,reset;
input [127:0] Key;
output [127:0] Out32;
reg [127:0] Out31= 128'h6353e08c0960e104cd70b751bacad0e7;



wire [127:0] Out01, Out11, Out21;
wire [127:0] Out02, Out12, Out22, Out32;

genvar i;
generate
for (i=0;i<=3;i=i+1)begin




MixColumn mc1(Out31[i*32+:32], clk, Out32[i*32+:32], reset);
end

endgenerate

endmodule

module MixColumn(In, clk, Out,reset);
input [31:0] In;
input clk,reset;

output reg [31:0] Out=0;
reg [7:0] c00=0,c10=0,c20=0,c30=0;

reg [7:0] out00=0,out10=0,out20=0,out30=0;

always@(posedge clk)
begin
if (reset)
begin

c00 = In[31:24];
c20 = In[23:16];
c30 = In[15:8];
c10 = In[7:0];

case ({c00[7], c10[7]})

2'b00 : out00 = (c00 << 1) ^ (c10 << 1) ^ c10 ^ c20 ^ c30 ;
2'b01 : out00 = (c00 << 1) ^ (c10 << 1) ^ 8'h1b ^ c10 ^ c20 ^ c30 ;
2'b10 : out00 = (c00 << 1) ^ 8'h1b ^ (c10 << 1) ^ c10 ^ c20 ^ c30 ;
2'b11 : out00 = (c00 << 1) ^ 8'h1b ^ (c10 << 1) ^ 8'h1b ^ c10 ^ c20 ^ c30 ;
//default:
endcase

case ({c10[7], c20[7]})
2'b00 : out10 = c00 ^ (c10 << 1) ^ (c20 << 1) ^ c20 ^ c30 ;
2'b01 : out10 = c00 ^ (c10 << 1) ^ (c20 << 1) ^ 8'h1b ^ c20 ^ c30 ;
2'b10 : out10 = c00 ^ (c10 << 1) ^ 8'h1b ^ (c20 << 1) ^ c20 ^ c30 ;
2'b11 : out10 = c00 ^ (c10 << 1) ^ 8'h1b ^ (c20 << 1) ^ 8'h1b ^ c20 ^ c30 ;
//default:
endcase

case ({c20[7], c30[7]})
2'b00 : out20 = c00 ^ c10 ^ (c20 << 1) ^ (c30 << 1) ^ c30 ;
2'b01 : out20 = c00 ^ c10 ^ (c20 << 1) ^ (c30 << 1) ^ 8'h1b ^ c30 ;
2'b10 : out20 = c00 ^ c10 ^ (c20 << 1) ^ 8'h1b ^ (c30 << 1) ^ c30 ;
2'b11 : out20 = c00 ^ c10 ^ (c20 << 1) ^ 8'h1b ^ (c30 << 1) ^ 8'h1b ^ c30 ;
//default:
endcase

case ({c30[7], c00[7]})
2'b00 : out30 = (c00 << 1) ^ c00 ^ c10 ^ c20 ^ (c30 << 1) ;
2'b01 : out30 = (c00 << 1) ^ c00 ^ c10 ^ c20 ^ (c30 << 1) ^ 8'h1b ;
2'b10 : out30 = (c00 << 1) ^ 8'h1b ^ c00 ^ c10 ^ c20 ^ (c30 << 1) ;
2'b11 : out30 = (c00 << 1) ^ 8'h1b ^ c00 ^ c10 ^ c20 ^ (c30 << 1) ^ 8'h1b;
//default:
endcase

Out[31:24] = out00;
Out[23:16] = out10;
Out[15:8] = out20;
Out[7:0] = out30;

end

end
endmodule
 

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