A Johnson counter in VHDL

jorge jesse cantu said:

with the following specifications:

Update: I did something dumb and posted the wrong code first, here is the right code:

design a 4-bit johnson counter and decoding for all eight states using just four flip-flops and eight gates. Your counter needs not be self-correcting.


i wrote my vhdl code for the 4-bit johnson counter, but i am confused as to what it means by decoding for all eight states, using eight gates? Do i need to have combinational logic to implement this? If so, how would i implement that in vhdl?

Here is my code:

HTML:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity json_cnter is
port ( 
        q : Out std_logic_vector(3 downto 0);
        rst : In std_logic;
        clk : In std_logic
        );
end json_cnter;

architecture behavior of json_cnter is

signal shft_r : Std_logic_vector (3 downto 0);-- :=(others => '0');

begin
q <= shft_r;
process(clk)
begin
    if(clk'event and clk = '1') then
        if (rst = '1') then
            shft_r <= (others => '0');	
        else
            shft_r(1) <= shft_r(0);		--shift bits to the right
            shft_r(2) <= shft_r(1);
            shft_r(3) <= shft_r(2);
            shft_r(0) <= not shft_r(3);
        end if;
    end if;
end process;
    
end behavior;

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