ash72
Newbie level 5
The spec : "A grant must at some time have been preceded by a request".
In order to write an assertion for this spec, I was given a solution in VHDL, as follows:
past_req <= req or past_req when rising_edge(clk);
assert_grant_follows_request : process(clk, reset)
begin
if rising_edge(clk) and reset = '0' then
assert grant = '0' or past_req = '1';
end if;
end process;
My question is what's the need for the signal "past_req"? Why is the assertion checking for grant in relation to past_req? Why not
assert grant = '0' or req = '1'? Has this something to do with delta delay?
Thanks.
In order to write an assertion for this spec, I was given a solution in VHDL, as follows:
past_req <= req or past_req when rising_edge(clk);
assert_grant_follows_request : process(clk, reset)
begin
if rising_edge(clk) and reset = '0' then
assert grant = '0' or past_req = '1';
end if;
end process;
My question is what's the need for the signal "past_req"? Why is the assertion checking for grant in relation to past_req? Why not
assert grant = '0' or req = '1'? Has this something to do with delta delay?
Thanks.
