A gate driver with limited swing

[kbx]

Hi,

I am working in a process with Vgs_max = 6V. However I have a supply of 7V. My input clock is 0-to-3V swing. What would be the best gate driver architecture to convert this input signal to drive a PMOS, such that its swing would be (approx) 1V-to-7V?

Thanks,
KBX

 

[KlausST]

Hi,

maybe an analog CMOS switch and a couple of resistors....

Without knowing about currents and frequency and so on ..... all we can do is guessing.

Klaus

 

[d123]

Hi,

A 1V to 3V Vgs fully-on NMOS with drain on 7V supply controlling the PMOS gate, used as a level-shifter, maybe.