A DNL Testing Problem, why could it happen

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abonic

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Hi gays,
I'm now testig the DNL of AD976A (a 100KSps SAR ADC) using the standard sinusoidal code density method. It turns out that too much counts appear near the zero-crossing point(4096th bin) in the bathtub curve, see the fig. This would result in a large DNL error in the specific bin, and is thus undesired.

can anybody help to explain it
 

The DNL would still meet the datasheet specification but is unlikely to be real. I rather expect a fault in your code.
 
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    abonic

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FvM said:
The DNL would still meet the datasheet specification but is unlikely to be real. I rather expect a fault in your code.
Click to expand...
Dear FvM,
I'v Checked the code, and there is nothing wrong with it. Actually, it is a universial code that is applied in many of our applications.
Could there be any else reason responsible for the error?
 

The major carry (01111....1 -> 10000...0) is always the
worst case for DNL when you have a weighted binary DAC
as part of the setup. This could well be real. It could also
be that there are some board level issues arising from the
logic code differences in ground current, if there is any.
There might also be some settling time component to this
if you are trying to run the ADC real fast, that point is where
everything in the circuit is being kicked. Might have a look
at the supply pin-pin, looping on 4095/4096 code.
 
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    abonic

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Dear dick & dominik, your suggestions are well inspiring. It is the board issues that deserve an overhaul. I'll do it later and post the results. Thank you.
 

Dear dick & dominik, the method provided by dick is pretty practical. In addtion, the packaged data from the raw ADC output was contaminated by an unexpected logic error during the packaging process.
The problem has been well settled. Thank you both of you guys
 

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