A/D-D/A sampling problems

Hello! This is my first post to this forum so nice to meet you. Well the fact goes like that:
For a project at university we are required to connect an ADC and DAC in order to create a circuit that will be able to sample the input and reproduce the input waveform in the DACs output. We chose to use ADC0805 and DAC0808 from National Semiconductors. We constructed the circuit and it works fine for DC inputs.
We set up the ADC to do continuous conversions with a clock frequency of 640kHz. The reference voltage is 5.12 V and the analog input can be up to 5V positive. We use as an input a fully-rectified sinus. Now i have two problems-questions:

1)The A/D can sample with a frequency of at leaste 6.5 MHz. The D/A has a worst-case settling time of 1.2 μS(833 kHz). That means that a signal with frequency under 400 kHz should be sampled perfectly! We can get a pretty good signal in the DAC output only for frequencies below 300Hz!!!

2)(and most improtant) When we increase the amplitude of the sinus applied to the A/D input over 1 V it is chopped!! Any ideas why this could happen??

Thanks in advance for any ideas!

The ADC needs a sample/hold in front of it to sample quickly changing signals. Are you using the right bias voltages on the ADC to allow the input signal range you need?

Check GND voltage, gain, and offset settings.

Thanks for the quick replies! Well... I use the right bias signal voltages. I thought the A/D would need a S/H for larger frequencies. Is a frequency of 600 Hz considered a quick changing signal? I thought the D/A was responsible for the low sampling rate... Anyway i will try it.
The offset,gain, and GND settings are ok. I mean...The circuit is functioning perfectly for DC input. The problem is with AC.

Check ADC sampling capasitor - it probably has high value than recommended .

what do u mean ADC sampling capacitor?

Assuming you do not use the circuit above , your adc has itnernal clock generator . check its fre

I did not work with this ADC but from datasheet you can check following
- this adc has itnernal clock generator , check its frequency on pin 19 . If it is too low - you wont be able to corectly get high freq .
- for chopping check the voltage reference on pin 9 .
(see 2.4 section of datasheet )

Above i assume that you do not use any external sample and hold circuit .

kgl_13gr

if I interpret the datasheet of the ADC correct it sais that it has a conversion time of about 100uS in default free running mode which is about 10 KHz.

Now using this factors you can calculate that you get about 16 samples for a 600 Hz signal which is really not much

You will also definitly need a sample and hold stage before your ADC because the input signal must not change during the 100 uS conversion time otherwise you will just get crap ...

To avoid these problems you will need a Flash ADC similiar to this principle schematics:

https://www.allaboutcircuits.com/vol_4/chpt_13/4.html

Flash ADC's "instantly" capture signals and also do not need sample and hold stages.

hope this helps, best regards

artem:

I use a Vref of 5.12 V and the input signal gets chopped at about over 1 V!!!

The frequency of the internal cock is 640kHz. In the free running mode the ADC samples with a frequency of about 7-8000 samples/sec. So i dont see why this could cause the problem.

C-man:

You are pretty right! I was just thinking that the sampling frequency was above the Nyquist frequency and thought i could get a perfect output signal. But you are right! They are just 16 samples! I suppose to rebuilt your signal totally u need some other techniques too...

Can the signal be chopped due to the absence of a S/H circuit? I dont see the reason. Anyway i will add a S/H.

Something else I noticed. The ADC has two grounds. Analog and Digital GND. In the circuit i connected them together to the ground of the DC power supply. Could that be the cause of the problem?

Thank you all for your interest!

kgl_13gr said:

Can the signal be chopped due to the absence of a S/H circuit? I dont see the reason. Anyway i will add a S/H.

Click to expand...

Yes of course. To understand the principle of successive approximation (used by your ADC) look here:
**broken link removed**

best regards

Problem Solved!!! It was pretty stupid i must admit. Well dont laugh at me i m just a beginner! I m learning!
The chopping was due to the fact that we were connecting the A/D to the negative output of the rectification bridge and the earth to the positive. So the negative signal applied to the A/D input was chopped i suppose by some protecting diode or something like that! Stupid eh?
As far as sampling is concerned we get adequate reproduction of the signal for frequencies under 600 Hz without S/H circuit. After all the above that C-Man said this is quite satisfactory for the requirements of the project.

Thank you all!