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I’m doing gate-level simulation recently, and I found a very curious problem when deposit Q value of some DFF cells. To illustrate my question briefly, I wrote a simple testbench, please refer attached file(you should decompress it first).

In this testbench, there is a DFF cell without reset. It has only 3 signal ports – CK, D, and Q.

At 600ns, CK is stopped;

At 700ns, D changed to 0. Because clock is not available, Q did not change to 0.

At 1000ns, Q is deposit to 0 by verilog task $deposit.

At 1100ns, D changed to 1.

At 1235ns, CK is resumed. But at this time, Q does not change to 1. This is very curious! I suppose Q should change to 1, but it did not.

It seems that simulator has bug! Does anyone know why that is？

Many thanks!

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