a crystal circuit problem,help!

[jjww]

crystal circuit design

One pin 455K OSC resonance circuit:

circuit description:
this circuit used to generate a 455KHz clock signal from 2v to 5v, the crystal one pin connects to the osc pin,the other pin connects to GND.when the output of I128 changes from one to zero, this circuit starts to oscillate a 455KHz clock signal, while it changes from zero to one, the circuit stop oscillating.
question:
when 2v=<VDD<3.6v, this circuit generate a frequency of 455KHz, which is the parallel resonance of the crystal that connected to the OSC pin; but when VDD increases higher than 3.6v, this circuit generates a frequency of 6MHz, what is the reason of this phenomena, and how can I adjust the parameter of this circuit to make the circuit always generates a 455KHz signal from 2v to 5v, the relation between the frequency of the internal RC circuit,which constructured by I130、I38、M9、R5、R6、R7 and the frequency of the external crystal should be what? I expect some kind-hearted friends to help me.

 

[dick_freebird]

455k crystal

You are skipping to a high overtone mode I would
guess (many crystals are designed for overtone use,
but this is probably an unintended thing here).

You might want to begin with better supply decoupling
around the IC and making sure the crystal "ground"
leg, is as tight as possible layout-wise to the IC ground
pin that matters most to the oscillator input circuitry
(any ground-bounce could inject the kicks for the
overtone mode, so the crystal wants to not be on
the main current loop etc.). The chip supply AC blips
are one thing that worsens with increased VDD.