A common-source stage with R and C to oscillate

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electronics20

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Hi all
I want to simulate a simple oscillator, which is attached, by hspice, but the output does not oscillate.
please help me to set R,C and W/L in 350nm.
Many thanks
 

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  • OS.jpg
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Try to use a ramp for the VDD source starting at 0V and finishing at VDD. Usually oscillators need a little nudge to get them started .

BR Jerry
 

electronics20 said:
Hi all
I want to simulate a simple oscillator, which is attached, by hspice, but the output does not oscillate.
please help me to set R,C and W/L in 350nm.
Many thanks
Click to expand...

This phase shift oscillator needs a gain of (at least) A=-29 .
My recommendation: Check the gain stage (dc operating point) and - if necessary - shunt also R1 with the capacitor.
 

To fullfil the oscillation condition for an unbuffered equal RC phase shift network, the amplifier must have a gain of 8. Transistor gm and resistor values should be chosen respectively. You can mesure the loop gain to verify that the circuit is able to oscillate. The loop can be easily opened at the gate.

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Gain of 8 was copied from an erroneous paper, 29 seems right, of course inverted.
 
The phase shift oscillator is very finicky to get going.

I cannot get my simulation to work with a mosfet.

I suggest you use a transistor instead of a mosfet. The transistor bias voltage has a narrow range of operation. Small variations produces big changes.

(A mosfet has a wide range of operation.)

Add an adjustable bias via potentiometer.

Careful adjustment is needed, to find the right point where oscillations can be sustained.
 
BradtheRad said:
I suggest you use a transistor instead of a mosfet.
Click to expand...

Ohh - I am afraid, this would complicate the situation as the transistor bias network as well as the input resistance into the base must be taken into consideration.
The advantage of the FET is
- its very high input resistance which can be neglected
- and that no bias circuitry is necessary.
 
my hspice file with Jfet is as follows:
*oscillator
.op
R1 IN 0 10k
R2 1 4 10k
R3 4 0 10k
R4 2 0 10k
R5 3 0 10k
R6 oUT VDD 10k
j1 oUT IN 1 J2N3819
C1 1 2 200p
C2 2 3 200p
C3 3 IN 200p
C4 4 0 200p
vDD1 VDD 0 20
.TRAN 1u 10m

.model J2N3819 NJF(Beta=1.304m Rd=1 Rs=1 Lambda=2.25m Vto=-3
+ Is=33.57f Cgd=1.6p Pb=1 Fc=.5 Cgs=2.414p Kf=9.882E-18 Af=1)

.END



but it still does not oscillate!
 

How to assign loop gain by hspice?
Click to expand...
The circuit has no DC feedback, so you can cut the loop, place a voltage source at the gate and measure the voltage at the resistor beneath the gate terminal.

A meaningful bias point must be presumed, it will only work with a depletion mode transistor. Otherwise you need to apply a positive gate bias voltage.

I agree with Brad that implementing sufficient gain with a FET can be tricky, it's however possible. I made an example with a JFET in LTSpice.



- - - Updated - - -

my hspice file with Jfet is as follows
Click to expand...
By using equal resistors for R2 and R6, the amplifier gain is already below unity, oscillation is simply impossible. In addition, the oscillator needs some kind of kick-start, as mentioned in post #2. I'm doing it with the "skip initial transient solution" option (uic).
 

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  • FET_Phaseshiftosc.zip
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Dear all
Many Thanks for ur helps.

- - - Updated - - -

Another question for BJT plz, how to simulate previous circuit by BJT? what's the amount of C and R?
 

FvM said:
I agree with Brad that implementing sufficient gain with a FET can be tricky, it's however possible. I made an example with a JFET in LTSpice.
Click to expand...

If it is a problem to provide a gain of -29 with the FET, why not using 4 C-R sections (instead of three)?
In this case, the required gain is reduced to (approximately) -18.
 
Keeping most of the original dimensioning, you get this circuit. In contrast to the FET amplifier where gm is a function of √Id and the currents and impedances can't be easily scaled, you can scale all resistors and capacitors by a factor (capacitors inversely) and get similar behaviour of the BJT circuit. That's up to you.

 

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  • BJT_Phaseshiftosc.zip
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electronics20 said:
Another question for BJT plz, how to simulate previous circuit by BJT? what's the amount of C and R?
Click to expand...

As mentioned already, the design is more complicated because the BJT input resistance and the bias circuitry are to be included in the calculation.
 
If it is a problem to provide a gain of -29 with the FET, why not using 4 C-R sections (instead of three)?
In this case, the required gain is reduced to (approximately) -18.
Click to expand...
That's possible of course. In the shown circuit, you can create a phase leading effect by placing a smaller source bypass capacitor which also reduces the required amplifier gain.
 
electronics20 said:
Another question for BJT plz, how to simulate previous circuit by BJT? what's the amount of C and R?
Click to expand...

Here is my simulation using an NPN transistor.



By careful adjustment, it can start oscillating immediately (in theory).

This is Falstad's animated interactive simulator. It can export a link which will:

(a) open the website www.falstad.com/circuit
(b) load my schematic into the simulator, and
(c) run it on your computer.

Link:

https://tinyurl.com/oe4c8qa

It portrays current intensity and direction. The numerous scope traces are especially informative.

You can change values at will. Right-click on a component, and select Edit.

Mosfets and JFET's are also among the supported components. I did not try a JFET yet.
 
C3 in post #16 has a much lower load resistance than the other two capacitors caused by the low input resistance of the transistor (about 1.2k ohms) and the bias resistor. But the RC networks load each other down so much then maybe it doesn't make much difference.
 
Thanks, but I need this circuit in HSPICE environment, so needing BJT model and etc.
 

A phase-shift or Bubba oscillator works MUCH better when opamps are used instead of transistors.
Because an opamp has a very high input impedance and a very low output impedance.
 
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