Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
manual cloning is cumbersome and then placement as well.
Buffering nowadays is well -done by all products today at syntyhesis and post placement optimization stages.
Cloning is better done when you ahve physical information and can help break down the fanout also and then place the cloned instance near to the rest of the logic that it is talking to
a quick thought tells me buffering offers two main advantages / need - High fanout fixing and addressing drive strength
Cloning also helps high fanout but this ideally should be more placement aware or area aware. For eg if you have a high fanout whose loads are at two ends of the placeable area then a clone at two ends of these loads helps address high fanout + congestion, timing and routing.
most common is the clock gates clone / declone which helps address CG setup times.
i think the answer is in my earlier append itself - pls note that it does mean that buffering will not be able to solve the high fanout issue if the loads are placed at two different ends - it may but it may add as an overhead to routing resources, congestion. Also will it be optimal adding many buffers across.
My best take would be clone logic in this case and save the above resources instead of adding many buffers. As i mention - cloning also addresses high fanout but this opto trick is more placement / physical aware
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
