90 nano design issues

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hi
have any one worked on 90 nano.. wht kind of issues one need to handle
while designing the layout for a 90 nano design. is any one aware of certain issues or guidline for this.
kindly let me know thanks in advance
tama
 

I think that leakage current is the main concern. Especially the Ioff can go up to uA.
 

so in general, there are high vt and low vt process for you choose.
 

i would like to know some source to learn layout in 90nm design.?
how to take care of leakage current ?
 

i remeber there are a book published by Kluwer
It is published in 2004
but the name i dont remeber,
maybe you can have a try to search
 

usually leakage control scheme should be taken care during circuit design. As mentioned by mists, two Vt process is one of the method to reduce the leakage. However, in term of layout, not much u can do about it, mayb reducing the parasitic effect will help.
 

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