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This is fundamentally a PLL design using XOR as the phase mixer with 2F and DC out.

The OTA variable R, fixed C as the analog phase shifter rather than a VCO.

The error amplifier is an integrator in most PLL's unless there is a critical stability or speed requirement for jitter, phase noise then more complex PID filters are  used.

I added a 2nd order LPF to reduce the AM and PM effects of V(ctrl) ripple.

But that also reduces phase margin in the loop and introduces some sub- harmonic resonance that is hard to see with my values but depending on the amount of overkill on V(Ctrl) filtering that may be between 5% to 30% of the signal frequency and result in returning the AM/PM jitter in a repeating longer period than just 1/2f. Since the variable OTA resistance control the current in R7, changes the phase shift and amplitude, it  also shifts the pole and the unity gain point where phase margin is measured.  I did not attempt to optimize it with a Kd gain aka lead-lag compensation filter, as it appeared good enough after 100 ms startup and I know you were in no rush to switch frequencies.   Frank's initial design you may judge as adequate, my changes are just small reductions in amplitude error.

 I did try an FM sweep using 12.5 kHz carrier 100% modulation at 50 Hz to see the tracking and it looked good ( although only about 10kHz to 40 kHz) changing the non-linear FM parameters when swept too low below 5kHz could cause U5 to clip to -15V which means the loop gain suddenly becomes "zero".  Then the 50 Hz sine V(ctrl) looks a but ragged swinging at the negative peak.  Some adjustments may prevent this but a 1 decade span seems to be the limit for a single stage OTA in a dual chip unles you avoid overshoot with the PID optimization. But you are just static tuning, so no worries.