Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

[SOLVED] 9-input NAND gate problem

Status
Not open for further replies.

ylhsheep

Newbie level 1
Newbie level 1
Joined
Feb 11, 2012
Messages
1
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,288
Many 9-input NAND gate are present in a mixed signal IC chip under analysis. In my opinion, the nmos in series of the NAND will not turn on, for the VDD is 5V,and the threshold voltage of the low-threshold nmos is about 0.65V. So how to apprehend the function of the 9-input NAND gate.
 

I don't see immediately how the NMOS series connection should cause other problems than making the device slow.
 

Assuming the nand gate is not sinking dc current, the final voltage drop across the drain-source of the NMOS will be zero, so each gate-source voltage will be the full supply. Thus the NMOS will all be on. However, like FvM says, it will be slow. This is because you have nine NMOS devices in series which have to be very big to keep the impedance low. The big devices will add extra capacitance.

rg
 
  • Like
Reactions: FvM

    FvM

    Points: 2
    Helpful Answer Positive Rating
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top