library IEEE;
use IEEE.std_logic_1164.all;
entity checksum8bit is
port (
serialnumber : in std_logic_vector (31 downto 0);
countervalue : in std_logic_vector(15 downto 0);
Finalsum : out std_logic_vector (7 downto 0)
);
end checksum8bit;
architecture behavioral of checksum8bit is
-- signal, component etc. declarations
component checksum
port( DataA : in std_logic_vector(7 downto 0);
DataB : in std_logic_vector(7 downto 0);
Sum : out std_logic_vector(7 downto 0)
);
end component;
BEGIN
process
VARIABLE SUM1 : STD_LOGIC_VECTOR (7 DOWNTO 0) := "00000000";
VARIABLE DATAPAC(1) : STD_LOGIC_VECTOR (7 DOWNTO 0) := SERIALNUMBER(31 DOWNTO 24);
VARIABLE DATAPAC(2) : STD_LOGIC_VECTOR (7 DOWNTO 0):= SERIALNUMBER(23 DOWNTO 16);
VARIABLE DATAPAC(3) : STD_LOGIC_VECTOR (7 DOWNTO 0):= SERIALNUMBER(15 DOWNTO 8);
VARIABLE DATAPAC(4) : STD_LOGIC_VECTOR (7 DOWNTO 0) := SERIALNUMBER (7 DOWNTO 0);
VARIABLE DATAPAC(5) : STD_LOGIC_VECTOR (7 DOWNTO 0):= COUNTERVALUE(15 DOWNTO 8);
VARIABLE DATAPAC(6) : STD_LOGIC_VECTOR (7 DOWNTO 0):= COUNTERVALUE (7 DOWNTO 0);
begin
for I in 1 to 6 loop
checksum_1: checksum port map (
DataA => sum1
DataB => DATAPAC(1),
sum => sum1
end loop;
end process;
Finalsum <= sum1;
end behavioral ;