Before designing 512K memory design, I have a problem during design 8bit memory.
I am doing layout with Cadence Virtuoso. I had done layout 1bit cell first. And made 2bit cell with 2 instance of 1bit cell, 4bitcell with 2 2bitcell and 8bitcell with 2 4bitcell.
Finally, doing LVS with calibre(hierarchy), I had problem. It is that some transistor in 1bitcell is disapeared and moved to 8bitcell(top view).
Is there any reason the transistor in bottom level to move to top level hierarchy?
And in hierarchy design is it ok to intersect between two instance?