Problem with UART in VHDL (Spartan 3E)

[lythanhthuan]

I am working to FPGA(spartan 3) and i decided to form a simple vhdl code that sends to computer arbitrary data then i will try to add receiving part then extra something but whatever i do i couldnt manage it. plzz help me
My code is following i used no parity and baud rate 9600. my board clock is 50 MHz )

  library IEEE; 
use IEEE.STD_LOGIC_1164.ALL; 
use IEEE.STD_LOGIC_ARITH.ALL; 
use IEEE.STD_LOGIC_UNSIGNED.ALL; 


library UNISIM; 
use UNISIM.VComponents.all; 

entity main is 
generic(baud : std_logic_vector(12 downto 0):="1010001011000"; -- clock divider for baud rate 
clk_increment : std_logic_vector(12 downto 0):="0000000000001"; 
shift_increment : std_logic_vector(5 downto 0):="000001" 
); 
Port ( sseg : out std_logic_vector(3 downto 0); 
display : out std_logic_vector(6 downto 0); 
tx : out std_logic; 
rx : in std_logic; 
clk : in std_logic; 
switch : in std_logic); 
end main; 

architecture Behavioral of main is 
component OBUF_LVCMOS33 port 
( O : out std_logic; 
I : in std_logic); 
end component; 
component IBUF_LVCMOS33 port 
( O : out std_logic; 
I : in std_logic); 
end component; 
component ibufg port 
( O : out std_logic; 
I : in std_logic); 
end component; 
component bufg port 
(i : in std_logic; 
o : out std_logic); 
end component; 


signal s_sseg : std_logic_vector(3 downto 0); 
signal s_switch : std_logic; 

signal s_disp : std_logic_vector(6 downto 0); 
signal s_rx,s_tx: std_logic; 
signal clk0:std_logic; 
signal baud_fixer : std_logic_vector(12 downto 0):="0000000000000"; 
signal data_counter : std_logic_vector(5 downto 0):="000000"; 
signal baud_generator : std_logic:='1'; 
signal bit_clock : std_logic; 
signal data_format: std_logic_vector(9 downto 0); 
signal data :std_logic_vector(7 downto 0):="01100001"; 
signal data_to_send :std_logic:='1'; 

begin 

segcom : FOR i IN 0 to 3 generate 
seg0 : OBUF_LVCMOS33 port map 
(O => sseg(i), 
I => s_sseg(i)); 
end generate segcom; 
switchcom : IBUF_LVCMOS33 port map 
(O => s_switch, 
I => switch); 
dispcom : FOR i IN 0 to 6 generate 
disp0 : OBUF_LVCMOS33 port map 
(O => display(i), 
I => s_disp(i)); 
end generate dispcom; 
rxcom: IBUF_LVCMOS33 port map 
(O => s_rx, 
I => rx); 
txcom: OBUF_LVCMOS33 port map 
(O => tx, 
I => s_tx); 
clkcom: ibufg port map 
( O => clk0, 
I => clk); 
bitgen: bufg port map 
(i => baud_generator, 
o => bit_clock); 


s_sseg<="1001"; 
s_tx<=data_to_send; 
-- baud rate generator 
process(clk0) 
begin 
if clk0='1' then 
if baud_fixer<=baud then 
baud_fixer<= baud_fixer+clk_increment; 
else 
baud_fixer<="0000000000000"; 
baud_generator<= not baud_generator; 
end if; 
end if; 
end process; 

-- data shifter 
data_format(0)<='0'; 
data_format(9)<='1'; 
data_format(8 downto 1)<= data(7 downto 0); 
process(bit_clock) 
begin 
if s_switch='0' then 
s_disp<="0100100"; 
if bit_clock='1' and bit_clock'Event then 
if data_counter<"001001" then 
data_to_send<=data_format(conv_integer(data_counter)); 
data_counter<=data_counter+shift_increment; 
elsif data_counter>="001001" and data_counter<"011100" then 
data_counter<=data_counter+shift_increment; 
data_to_send<=data_format(9); 
else 
data<=data+"00000001"; 
data_counter<="000001"; 
data_to_send<=data_format(0); 
end if; 
end if; 
else 
data_to_send<='1'; 
data_counter <="000000"; 
s_disp<="0111111"; 
end if;

 

[BuBEE]

UART with VHDL

TRY UART From xilinx it's good.

 

[ds18s20]

Re: UART with VHDL

TRY UART From xilinx it's good.

Anyone has the same code in Verilog? I have seen examples in Verilog for UART but they are super complex. I am looking for something simple so that it can be used as the most basic foundation for teaching Verilog?

 

[yasser_shoukry]

Re: UART with VHDL

I have downloaded a verilog one before, but i forgot its site, any how here it is, hope it helps

 

[ds18s20]

Re: UART with VHDL

Thanks yasser_shoukry

This was pretty much what I neede. The main .v file looks pretty simple - just what I was looking for

~B