8 point fft using ipcore

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module tb;
 
always
begin 
clk =1;
#10;
clk =0;
#10;
end
 
    // Inputs
    reg clk;
    reg start;
    reg [31:0] xn_re;
    reg [31:0] xn_im;
    reg fwd_inv;
    reg fwd_inv_we;
 
 
    // Outputs
    wire rfd;
    wire [2:0] xn_index;
    wire busy;
    wire edone;
    wire done;
    wire dv;
    wire [2:0] xk_index;
    wire [31:0] xk_re;
    wire [31:0] xk_im;
 
    // Instantiate the Unit Under Test (UUT)
    fft1 uut (
        .clk(clk), 
        .start(start), 
        .xn_re(xn_re), 
        .xn_im(xn_im), 
        .fwd_inv(fwd_inv), 
        .fwd_inv_we(fwd_inv_we),
        .rfd(rfd), 
        .xn_index(xn_index), 
        .busy(busy), 
        .edone(edone), 
        .done(done), 
        .dv(dv), 
        .xk_index(xk_index), 
        .xk_re(xk_re), 
        .xk_im(xk_im)
    );
 
    initial begin
        // Initialize Inputs
        clk = 0;
        start = 0;
        xn_re = 0;
        xn_im = 0;
        fwd_inv = 0;
        fwd_inv_we = 0;
        
        // Wait 100 ns for global reset to finish
        #100;
        
        start = 1;
        fwd_inv = 1;
        fwd_inv_we = 0;        
        // Add stimulus here
        
       //#20;
        xn_re = 32'b01000000000000000000000000000000; // 2
      xn_im = 0;        
        
        #20;
        
        xn_re = 32'b01000000100000000000000000000000; //------ 4
        xn_im = 0;
        
        //#20;
        
        //xn_re = 32'b01000000111000000000000000000000; //------ 7
        //xn_im = 0;
        
        //#20;
        
        //xn_re = 32'b01000001000100000000000000000000; //------9
        //xn_im = 0;
 
       //#20;
        //xn_re = 32'b01000000010000000000000000000000; //------ 3
        //xn_im = 0; 
        
        //#20;
 
        //xn_re = 32'b01000001001000000000000000000000; //------ 10
        //xn_im = 0;
 
      //#20;
 
      //xn_re = 32'b01000001010000000000000000000000; //------ 12
        //xn_im = 0;
 
     // #20;
 
      //xn_re = 32'b01000001011100000000000000000000; //------ 15
        //xn_im = 0;
 
 
        
    end
      
endmodule

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module fft1(clk,start,xn_re,xn_im,fwd_inv,fwd_inv_we,rfd,xn_index,busy,edone,done,dv,xk_index,xk_re,xk_im);
  
input [31:0] xn_re,xn_im;
input clk,start,fwd_inv,fwd_inv_we; 
 
 
output [31:0] xk_re,xk_im;
output [2:0] xn_index,xk_index;
output rfd,busy,done,edone,dv; 
  
reg ce=1,sclr=0; 
wire [31:0] xk_re,xk_im;
 
 
fft1_ip a1(
 
  .clk(clk), 
  .start(start),
  .ce(ce),
  .sclr(sclr),  
  .xn_re(xn_re), 
  .xn_im(xn_im), 
  .fwd_inv(fwd_inv), 
  .fwd_inv_we(fwd_inv_we),
  .rfd(rfd), 
  .xn_index(xn_index),
  .busy(busy), 
  .edone(edone), 
  .done(done), 
  .dv(dv), 
  .xk_index(xk_index), 
  .xk_re(xk_re), 
  .xk_im(xk_im) 
  
 );
 
endmodule