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-- Company:
-- Engineer:
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity nmod is
port( clear: in std_logic;
load: in std_logic;
arst_l: in std_logic; --make it active low
clk: in std_logic;
din: in std_logic_vector(7 downto 0);
count: out std_logic_vector(7 downto 0)
);
end nmod;
architecture Behavioral of nmod is
constant N: std_logic_vector(7 downto 0) := X"C0";
signal cout: std_logic_vector(7 downto 0);
signal arst: std_logic;
signal dain: std_logic;
begin
count <= cout; --output signal, output on left side
arst <= arst_l; --input signal, input on right side
process(clk, arst)
begin
if(arst = '1')then
cout <= '0';
elsif(clk'event and clk = '1')then
if(clear = '1' or cout = 'N') then
cout <= din;
else
cout <= cout +1;
end if;
end if;
end process;
end Behavioral;