8 Bit ALU Verilog Code

ads-ee said:

Do you have any idea what a mulitplexer is? Do you know what the truth table of a multiplexer looks like? Can you convert a truth table to a boolean expression? If not then you've got more of a problem understanding hardware and logic design than a problem with Verilog.

Verilog isn't "hard" it's just a way to represent hardware using text. It might be hard if you don't understand what the underlying hardware does.

You might want to invest in a book like this: https://www.amazon.com/Hdl-Chip-Design-Synthesizing-Simulating/dp/0965193438 It shows the synthesized logic for the RTL code for both VHDL and Verilog.

regards

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ads-ee said:

The majority of learning how to code in Verilog is just learning what the synthesis tools will do with your code and what the resulting circuit looks like. That is why there are suggested methods of writing Verilog/VHDL to represent various logic blocks like: registers, mulitplexers, selectors, etc.

https://asic-world.com/examples/verilog/index.html
has a bunch of examples of writing various constructs in Verilog.

Regards

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pbernardi said:

No, you can add all the operations in the same file. Let´s say:

Code:

module ALU (
  input        [1:0] OP ,
  input              CLK,
  input        [7:0] A,
  input        [7:0] B,
  output reg   [7:0] OUT
);

wire [7:0] MUX [0:3];

assign MUX[0] = A + B;
assign MUX[1] = A - B;
assign MUX[2] = A ^ B;
assign MUX[3] = A & B;

always@(posedge CLK)
begin
  OUT <= MUX[OP]
end

I made the code withou testing (I have no ISE in this machine), but it should work.

But you *can* use several independent operations to make a bigger component, it is up to you. When to use a bigger component or when use several small modules? I suggest thinking in ICs. For example, If you think you should have one IC for add, one IC for sub, etc., you should use several small modules. If you think you can make an IC with add, sub, xor, and, then you should make one single module. Got it?

Also, you can add the test bench in the same file as well. You just have to be sure to assign the correct module as top level (not the simulation module)

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