8-Bit ADC Issue With Residue Waveform

[ljp2706]

Hello,

Currently, I am trying to design an 8-Bit Pipelined ADC. What I have completed so far is:
4 Bit FLASH ADC
4 Bit Resistor String DAC
Sample and Hold Circuit
Summation and Gain stage

My reference voltage is 0V, VDD=1V, VSS=-1V.

For the sample and hold circuit, I have a near minimum sized Transmission gate switch connected to a capacitor, the output is buffered using the embedded source unity gain buffer in the image below.

For some reason, my residue waveform seems to be shifted up which results in missing bits for the second stage conversion(I've attached a simulation of this). The first 4 Bits in the first stage are working as expected.

While I do think that the gain stage is responsible for the fact that the residue plot is not across the full scale voltage range, I do not think it is responsible for the vertical shift in the plot. I used an ideal source(voltage controlled voltage source) and this still occurs. What is causing this issue? I have been unable to isolate it.



















Thank you!

 

[ljp2706]

If anyone was curious, I think I figured out the issue.

I think the offset of the amplifier is what is causing the shift. As the common mode voltage increases the gain slightly increases and the offset is amplified more.

Does anyone know what a good topology for offset cancelation, gain, and subtraction would be?

I am looking into some sort of switched capacitor implementation.

 

[Audioguru]

The moment a negative (Cadence?) schematic appears on my screen I turn it off. Why does Cadence make an awful looking negative instead of a positive image like everyone else?
Have you ever seen a negative image on a datasheet?

 

[KlausST]

@Audioguru,

Sometimes I "create" negative images to show some sample values for custom measurement tools..
Mostely when a customer is used to work with (old) scopes.
With those scopes it is usual that the background is dark, while the beam is bright.

But I agree nowadays one should use bright background with colored lines.

Is it possible to adjust the cadence's background?

Klaus

 

[ljp2706]

Yes, it is very easy to do so too.

1.) Zoom into the portion of the circuit you want to take a picture of
2.) File->Export Images
3.) Set the background as white
4.) Save or copy file

I personally think it is easier to see the negative on the screen, but when I print it, I use this method.

 

[Audioguru]

I complain about negative Cadence images because it causes a thumbnail image to be invisible and when enlarged the text is difficult to see.

 

[KlausST]

Hi,

Does anyone know what a good topology for offset cancelation, gain, and subtraction would be?
I am looking into some sort of switched capacitor implementation.

The switched capacitor solution is on the analog side and needs some hardware effort, so this increases the cost if every singke device.
If the drift of the offset without switched capacitors is low enough, then i'd say a software solution by simply adding/subtracting a digital value is the cheaper solution.

Klaus

 

[ljp2706]

I ended up doing the switched capacitor method and it works well. My issue now is that the signal does not track well near the negative rail (Input common mode range issue)...What can I do to increase the gain near VSS?

Vdd=1V Vss=-1V

As of right now, at the 0V I have 55dB, at -0.5v I have 54dB and at -1V I have 2dB. I would like to get this up to at least 10dB, but I am not sure how to do it. My overdrive voltages of the active load are extremely small. The amplifier topology used is a simple differential amplifier with common source second stage. Would there be a better topology for this?