celebrevida
Member level 2
I need to design an 8-bit, at least 10MSample/s ADC.
I don't have access to a clk with stable frequency (can only generate an internal clk via ring oscillator which is highly variable). Thus any time-based VTC/TDC design requiring a stable clk is out.
Flash ADC requires large 255-tap resistor ladder and 255 comparators so seems impractical as far as area and power are concerned.
I also don't have a lot of time to get this done so complicated architectures would be out.
Best choice seems to be SAR ADC so far.
Is this the case or are there other architectures to consider? The simpler the better.
Thanks in advance!
I don't have access to a clk with stable frequency (can only generate an internal clk via ring oscillator which is highly variable). Thus any time-based VTC/TDC design requiring a stable clk is out.
Flash ADC requires large 255-tap resistor ladder and 255 comparators so seems impractical as far as area and power are concerned.
I also don't have a lot of time to get this done so complicated architectures would be out.
Best choice seems to be SAR ADC so far.
Is this the case or are there other architectures to consider? The simpler the better.
Thanks in advance!
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