Difference between Block RAM and Distributed RAM in FPGA

[richardyue]

block ram

What is the difference between block RAM and distributed RAM in FPGA? I'v read some application notes, but I'm still confued about these two RAMs.

 

[echo47]

xilinx block ram

In Xilinx FPGAs, a Block RAM is a dedicated two-port memory containing several kilobits of RAM. The FPGA contains several (or many) of these blocks.

Inside of each small logic block is a configurable lookup table. It is normally used for logic functions, but you can reconfigure it as a few bits of RAM. You can combine several (or many) of them into a larger RAM. This is distributed RAM.

Both types of RAM can be initialized with data, or used as ROM.

 

[richardyue]

distributed ram

The distributed RAM is within the LUT, and the Block RAM is outside the LUT. Am I right?

 

[echo47]

fpga block ram

Yes. Here are two relevant application notes.

"Using Block RAM in Spartan-3 Generation FPGAs"
**broken link removed**

"Using Look-Up Tables as Distributed RAM in Spartan-3 Generation FPGAs"
http://www.xilinx.com/bvdocs/appnotes/xapp464.pdf

Lots more nice app notes:
**broken link removed**

 

[richardyue]

block ram wiki

Another question: Let's say that if I want to design a adder using FPGA, we store the execution code in the FPGA, specifically in the LUT. Am I right? If I'm right, then how can FPGA keep the execution code? Because I think that LUT is a RAM, it is volatile. When it is powered off, it cannot store the execution code any more. Maybe it is not the most suitable example, but I think it can make me understand how FPGA works. Hope someone can help me out. Thanks in advance.

 

[echo47]

block ram vs distributed ram

Correct! The FPGA configuration is stored in RAM, so when you power-down, your design disappears. Next time you power-up, you must reload the configuration from non-volatile memory such as flash. Most FPGAs provide several ways to do this. If you are using a Xilinx FPGA, see the "Configuration" chapter in the data sheet.

 

[richardyue]

ram block

The non-volatile memeory can be located in the FPGA or outside the FPGA? I think it's like a computer architecture. The computer stores it's code the mainboard and loads the code into the CPU RAM from the mainboard when it is powered on. Am I right?

 

[echo47]

what is block ram

You must provide an external non-volatile memory (commonly a flash ROM device), or some other means to configure the FPGA after power-up. For details, see that "Configuration" chapter.

When a computer motherboard powers up, the CPU executes the BIOS boot code stored in a flash ROM chip. The boot code reads the operating system from the hard drive into main RAM, and then the CPU executes it from there.

Loading a configuration into an FPGA is a sequential process. It's very different from a CPU executing code from ROM.

 

[richardyue]

blockram

But they both load their excution code from a non-volatile memory into RAM after powering on. Am I right? I don't understand your last statement. Would you like to tell the difference between them in more detail? Thanks for taking time to help me with my question.

 

[echo47]

block ram xilinx

A CPU does not boot up by transferring ROM code into RAM. The CPU executes the code directly from ROM by fetching one instruction at a time, and doing whatever that instruction requires. (Let's ignore CPUs that provide instruction caching.)

When an FPGA powers-up, all its internal logic fabric is unconnected, so the FPGA is non-functional. You connect the logic fabric according to your design by setting millions of tiny control switches either ON or OFF. Each control switch enables or disables one small feature in the logic fabric. The control switches are arranged as a giant shift register. You "configure" the FPGA by shifting your long configuration bitstream into the shift register (that usually takes less than one second). Then those millions of control switches activate simultaneously, and the FPGA logic fabric becomes your design.

Are you familiar with how a PAL/PLD works? An FPGA is somewhat similar, but instead of having permanent fusible links, an FPGA has those control switches.

 

[richardyue]

fpga distributed ram

In fact, I am not familiar with how a PAL/PLD works in a system. When an PAL/PLD powers up, does it fetch instrustions from the outside ROM? I'm totally confused about how these logic devices work now. Would you like to recommend some books for me?

 

[echo47]

difference between distributed ram and block ram?

Ok, forget PAL/PLD! They are old technology anyway.

I have not seen a good modern book about FPGAs.
Have you seen this?
https://en.wikipedia.org/wiki/Fpga

 

[rsrinivas]

difference between block ram and distributed ram

PAL and PLA is programmable array logic
they consist of and and or arrays which can be programmed to a particular application.
as they are at particular logic levels after being programmed(high or lo) they give out the same values each u read them.

 

[richardyue]

distributed block ram

Hi, echo47,
Would you like to answer some basic questions of the VHDL and FPGA design for me in the near future? I need some experts to help me with the problems when learning the design FPGA or related. Sometimes, maybe some questions are very silly, hope you can help me with patience.

 

[archillios]

distributed ram vs block ram

FPGA become more and more complicated, especially for advanced application, due to very special architecure of FPGA. Even senior FPGA engineer need tech-support from altera or xilinx in our company, so i dont think learning by yourself is time-economic.

 

[moytroy]

what is distributed ram

hi,
in a symmetrical array FPGA(eg.Xilinx) block RAMs are dedicated elements
present inside FPGA. usually they run parallel inside FPGA. its possible to have
both single port as well as dual port block RAMs. In dual port block RAMs both the ports operate at different clock speeds.
Distributed RAMs are implemented within LUTs. each CLB inside a Xilinx FPGA contains two slices and each slice contains 2 LUTs and LUTs are amde of SRAM
which can accomodate 16 bits.
so, for small memory you use distributed RAMs and for large memory use
Block RAM

 

[richardyue]

xilinx block ram

Hi, archillios,
Thanks for you advice. But, you know, I want to find a position in the FPGA field and now I have no work experience. So I have to learn it by myself.

 

[mohammadyou]

Re: xilinx block ram

thank you for your discussion its very useful
i have question
how can i write some data in block ram ?
i want to store some data in fpga and when fpga execute use data
i am beginner in vhdl
and what is deference between constant and array in fpga ?