VHDL code for a T-Flip Flop

[fm_com_28]

t flip flop vhdl

Dear,
I want to write a VHDL code for a T-flip flop .can you help me with that.
regards

 

[Jayson]

vhdl code for t flip flop

Here's a T flip flop with reset

library ieee;
use ieee.std_logic_1164.all
entity tff is
  port(
        clk: in std_logic;
        reset: in std_logic;
        t: in std_logic;
        q: out std_logic
      );
enf tff;

architecture behave of tff is
  signal q_reg: std_logic;
  signal q_next: std_logic;
begin
 process
 begin
       if (reset = '1') then
          q_reg <= '0';
       elsif (clk'event and clk = '1') then
          q_reg <= q_next;
       end if;
 end process;

       
       q_next <= q_reg when t = '0' else
                 not(q_reg);

       q <= q_reg;
end behave;

A T flip flop has the following equation: Q+ = T`Q+TQ` which is basically a D flip flop with a XOR gate connected to D, with one input being T and the other the Q output.

-Jayson

 

[digi]

Re: vhdl code for t flip flop

can anyone give the vhdl code on how to convert integer to binary?
can it be done using the structural model?

 

[imbichie]

I think this wiil be work

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity int2bin is
generic (N : integer := 64);-- Number of binary bits
port (
clk : in std_logic;
int : in integer;
bin : out std_logic_vector(N-1 downto 0)
);
end int2bin;

architecture behavior of int2bin is

signal count:integer;
signal d : integer;
signal b : std_logic_vector(N-1 downto 0);

begin

process(clk)
begin
if (clk'event and clk = '1') then
d <= 0;
b <= (others => '0');
L0: for i in 0 to int loop
if (d = int) then
bin <= b;
exit L0;
else
d <= d+1;
count <= 0;
for k in 0 to N-1 loop
if(count = 0) then
if(b(k) = '0') then
b(k) <= '1';
count <= 1;
else
b(k) <= '0';
end if;
end if;
end loop;
end if;
end loop L0;
bin <= b;
else
bin <= b;
end if;
end process;
end behavior;

let me know if any error

 

[permute]

my_slv <= std_logic_vector(to_unsigned(my_int,my_slv'length));

there really isn't a applicable structural model. A module could be made, but it would simply do the above.

Also, realize that integers are defined as 32b signed values. (unsigned "positives" are limited to 31b). This is annoying as FPGA's now have the capability for > 32b math.