74LS163A Internal working as shown in the attached file

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Hello everyone,

I am trying to replicate the DM74LS163A in VHDL but as we can see in the attached file, the J and K inputs have bars on top, does this mean they are logically inverted?



Any help will be greatly appreciated.
 

Hi,

A signal with a bar means: it is low_active.

Compared with a high_active signal, the function is inverted.

Klaus
 

It would certainly be much easier and efficient to implement by a behavioral description of the whole IC took from a top view.
 

Most databooks state that the circuit diagram is merely representative of the actual IC design.

You should just refer to the truth table and implement it behaviorally in VHDL/Verilog to match the truth table functionality.
 

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