Jul 16, 2020 #1 M metalmisers Junior Member level 2 Joined Mar 4, 2012 Messages 22 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 1,457 Hello everyone, I am trying to replicate the DM74LS163A in VHDL but as we can see in the attached file, the J and K inputs have bars on top, does this mean they are logically inverted? Any help will be greatly appreciated.
Hello everyone, I am trying to replicate the DM74LS163A in VHDL but as we can see in the attached file, the J and K inputs have bars on top, does this mean they are logically inverted? Any help will be greatly appreciated.
Jul 16, 2020 #2 KlausST Advanced Member level 7 Joined Apr 17, 2014 Messages 25,756 Helped 4,906 Reputation 9,835 Reaction score 5,690 Trophy points 1,393 Activity points 172,624 Hi, A signal with a bar means: it is low_active. Compared with a high_active signal, the function is inverted. Klaus
Hi, A signal with a bar means: it is low_active. Compared with a high_active signal, the function is inverted. Klaus
Jul 17, 2020 #3 andre_luis Super Moderator Staff member Joined Nov 7, 2006 Messages 9,624 Helped 1,190 Reputation 2,399 Reaction score 1,213 Trophy points 1,403 Location Brazil Activity points 55,828 It would certainly be much easier and efficient to implement by a behavioral description of the whole IC took from a top view.
It would certainly be much easier and efficient to implement by a behavioral description of the whole IC took from a top view.
Jul 17, 2020 #4 ads-ee Super Moderator Staff member Joined Sep 10, 2013 Messages 7,944 Helped 1,823 Reputation 3,656 Reaction score 1,808 Trophy points 1,393 Location USA Activity points 60,208 Most databooks state that the circuit diagram is merely representative of the actual IC design. You should just refer to the truth table and implement it behaviorally in VHDL/Verilog to match the truth table functionality.
Most databooks state that the circuit diagram is merely representative of the actual IC design. You should just refer to the truth table and implement it behaviorally in VHDL/Verilog to match the truth table functionality.