74F74 introduces glitches. how to overcome this?

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neazoi

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Hello I divide an input signal by 4 using a 74F74. But it introduces some glitches as well.
Can I do anything to overcome this?
Using a 7fls14 Schmitt trigger makes things worst!
 

If you are you working at very high speed, you will need probably work with a synchronous design.

At standard counter based on cascaded FFs, the clock for the next one is the output from the previous one, and this means that a propagation delay of each device will be cumulatively accounted, generating transient logic states.
 

You have an asynchronous FF chain (ripple carry counter) and see glitches at the output of the second FF? What kind of glitches? Sounds inplausible regarding basic FF behaviour. May be it's just bad supply bypassing, or some kind of crosstalk.
 

Some years ago I had a bad batch of 74F74 chips which gave "bad" outputs. You should try some from a different batch. What you are doing should work without glitches no matter how fast you clock them (within spec). Make sure that each 74F74 has its own ceramic 0.1uf decoupling directly across the supply rails.
 

The first picture shows the glitches when no ground connection was made from the prototype to the measuring ports of the scope.
The second picture shows the reduced glitches when ground was connected. But they are still there, no matter if the 74F74 has a decoupling cap or not. In fact a decoupling cap distorts slightly the waveform.
This is the best waveform I can get so far, by feeding the 90 deg shifted outputs of the 74f74 to the scope through 33R resistors. Without these resistors the waveform is more distorted (not a good square wave), but the glitches dissapear. Could it be the loading of the 74f74 (1M scope probe)? The input frequency is about 500KHz so it will be of no concern to the 74F74. I have also tried 74HC74 and the waveform is more distorted.

I apologise for the big attachments (1.8Mb each).
 

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As said, you must change the circuit topology.
See bellow the comparing of 2 counters 0-15 employing synchronous and asynchronous approach:

Asynchronous

Synchronous


Note that at 2nd circuit, no delay occur.
 
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    neazoi

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Synchronous counters must be used where they are needed by the design requirements. But no requirements have been yet mentioned in this thread that demand for a synchronous design. May be neazoid forgot to tell it.

It would be good to a circuit for the waveforms in post #5. I don't yet see where you get 90° shifted waveforms in 4:1 divider with two FFs.

I apologise for the big attachments (1.8Mb each).
Click to expand...
They reduce to 150k each if you open and resave it (with reasonable compression parameters) in a image viewer like IrfanView.
 


I need this delay, I need 90 degrees phase difference, that is why this topology is used. Or am I missing something here?
 

I need this delay, I need 90 degrees phase difference, that is why this topology is used. Or am I missing something here?
Click to expand...

???? The ripple carry frequency divider circuit as shown by andre_teprom introduces a propagation delay but not 90° phase shift. It can't generate two signals of same frequency with phase shift as in post #5. What am I missing here? Please show your actual circuit.
 


Yes I apologise, the requirement it to have two square wave signals shifted by exactly 90 degrees between them, so these can be used in an I/Q mixer. It is more convenient to do it by a FF chain rather than an LC/RC network.
The output I/Q signals must be at 135KHz (just to get an idea of the low frequency)

- - - Updated - - -


Here is the 74F74 schematic.
Will it be able to generate two signals phased by exactly 90 degrees? If not that is great news to me, I thought it could be done this way.
To what delay do you refer in post #6?
 

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Thanks, I should have guessed it.

I believe there are no glitches in the post #5 waveform, just ground bounce and/or power supply noise.

Looks like insufficient/ineffective bypassing.
Or heavy capacitive output load, 1:1 passive probes or coaxial cable directly connected to the FF output.
 
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    neazoi

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All right I will try better connections.
What has been said about the synchronous and asynchronous design has made me curious.
Will the simple 74F74 chip connected the shown way, be able to divide by 4 and output two signals exactly shifted 90 degrees between them?
Exact phasing shift is important to I/Q mixers.
I worry about this propagation delay that was mentioned in post #6. If this is the case then the propagation delay of the first FF will delay the switching of the second, and the propagation delay of the second, will delay even more the signal output. If this is the case then accurate 90 degrees phase shifting will not be done, am I right?
 

In contrast to what has been suspected, your circuit is a synchronous design. And it should achieve exact 90° phase shift because both outputs have the same propagation delay between input clock and Q. It's important that both outputs have the same load capacitance.
 


Thank you
The outputs will drive two identical mixers (maybe SA612AN or SBL-types) so I think they should "see" the same load capacitance.
I hope the square wave can drive satisfactorily foth types of mixers, passive and active, althought I am concerner if it will be suitable for active types like SA612 or not.
 

I have simulated your circuit and it generates the waveforms you wanted without any glitches. The glitches that you show on post 5 are ground bounce. Decoupling will help with this, as will a proper ground plane.
 
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    neazoi

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To me the original "glitches" look like supply and ground bounce.
The 74F series was supposed to be fast and strong, so will push
more impulse noise into the rails. Decoupling completes the internal
/ external supply AC current loop, but output loading induced
spiking has a more roundabout path and may not be helped so
much; hainging a 'scope probe on the outputs can also make the
observed "noise" greater than the circuit has when you're not
poking it. A little series resistor on the probe tip (corner freq
equivalent time constant less than risetime) can show you
whether the issue is inherent, or Heisenberg related. You ought
to have a look at the chip dround and Vcc terminals under the
same conditions (including choice of ground-clip-point) to see
whether a lot of the noise has to do with board ground current
loops, too.
 
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    neazoi

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dick_freebird said:
A little series resistor on the probe tip (corner freq
equivalent time constant less than risetime) can show you
whether the issue is inherent.
Click to expand...

I think that this is the case. For the series resistors I included, if they where big, there was a knee in the rising edge near 5v and the glitches dissapeared. But the waveform was not a pure square (knee). If they where very small they had no effect (and also no effect on the spikes).

As far as I can understand, I should better design a PCB for the circuit rather than testing it with long (20cm) hanged unshielded wires to the stope probes...
Grounding paths are bad on the breadboard as well.
Have you got a good guide to propose (link) for PCB grounding and good techniques that should be followed in HF logic?

Thanks a lot.
 

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